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| ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? 1 ? ? ? ? ? ? device highlights flexible programmable logic ? 0.25 m five layer metal cmos process ? 2.5 v v cc , 2.5/3.3 v drive capable i/o ? up to 4,032 logic cells ? up to 583,008 system gates ? up to 347 i/o pins embedded dual-port sram ? up to thirty-six 2,304-bit dual-port high performance sram blocks ? up to 82,900 ram bits ? ram/rom/fifo wizard for automatic configuration ? configurable and cascadable programmable i/o ? high performance enhanced i/o (eio)? less than 3 ns tco ? programmable slew rate control ? programmable i/o standards: lvttl, lvcmos, pci, gtl+, sstl2, and sstl3 eight independent i/o banks three register configurations: input, output, and output enable advanced clock network ? nine global clock networks: one dedicated eight programmable ? 20 quad-net networks?five per quadrant ? 16 i/o controls?two per i/o bank ? four phase locked loops embedded computational units ecus provide integrated multiply, add, and accumulate functions. figure 1: eclipseplus block diagram memory - dual port ram memory - dual port ram pll pll pll pll embedded computational unit s hi g h s peed lo g ic cell s 583k gate s combining performance, density, and embedded ram eclipseplus family data sheet
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 2 table 1: eclipseplus product family members ql7100 ql7120 ql7160 ql71 8 0 max gates 292,160 373,440 558,464 662,208 logic array 40 x 24 48 x 32 64 x 48 72 x 56 logic cells 960 1,536 3,072 4,032 max flip-flops 2,670 3,692 7,185 9,105 max i/o 250 310 347 347 ram modules 20 24 32 36 ram bits 46,100 55,300 73,700 82,900 plls 4 4 4 4 ecus 10 12 16 18 packages pqfp (0.5 mm) 208 208 - - lfbga (0.8 mm) 280 280 280 280 pbga (1.0 mm) 484 484 484 484 pbga (1.27 mm) - - 516 516 ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 embedded computational unit (ecu) traditional programmable logic architec tures do not implement arithmetic fu nctions efficiently or effectively? these functions require high logic cell usage wh ile garnering only moderate performance results. the eclipseplus family architecture allows for functionality above an d beyond that achievable using programmable logic devices. by embedding a dynamicall y reconfigurable computational unit, the device can address various arithmetic functions efficiently. this approach offers greater pe rformance than traditional programmable logic implementations. the embedded block is implemented at the transistor level as shown in figure 2 . figure 2: ecu block diagram the eclipseplus ecu blocks ( table 2 ) are placed next to the sram circuitry for efficient memory/instruction fetch and addressing for dsp algorithmic implementations. up to 18 8-bit multiply-accumulate (mac) functions ca n be implemented per cycle for a total of up to 1.8 billion macs/s when clocked at 100 mhz. addi tional mac functions can be implemented in the programmable logic. table 2: eclipse ii ecu blocks device ecus ql7180 18 ql7160 16 ql7120 12 ql7100 10 a[0:15] b[0:15] sign2 sign1 cin s1 s2 s3 a b c d 3-4 decoder 8-bit multiplier 17 inc. cout 16-bit adder 17-bit register 2-1 mux 2-1 mux 3-1 mux q[0:16] clk reset dq 00 01 10 a[0:7] a[8:15] www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 4 the modes for the ecu block are dynamically re-progra mmable through the programmable logic as shown in table 3 . table 3: ecu mode select criteria instruction operation ecu performance a , -7 wcc b a. t pd , t su and t co do not include routing paths in/out of the ecu block. b. timing numbers represent -7 worst case commercial conditions. s1 s2 s 3 t pd t su t co 0 0 0 multiply 6.57 ns max 0 0 1 multiply-add 8.84 ns max 0 1 0 accumulate c c. internal feedback path in ecu rest ricts max clk frequency to 238 mhz. 3.91 ns min. 1.16 ns max. 0 1 1 add 3.14 ns max 1 0 0 multiply (registered) d d. b [15:0] set to zero. 9.61 ns min. 1.16 ns max. 1 0 1 multiply- add (registered) 9.61 ns min. 1.16 ns max. 1 1 0 multiply - accumulate 9.61 ns min. 1.16 ns max. 1 1 1 add (registered) 3.91 ns min. 1.16 ns max. ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 5 phase locked loops (plls) instead of requiring extra components, designers simply need to instantiate one of the pre-configured models (described in this section and listed in table 4 ). the quicklogic built-in plls support a wider range of frequencies than many other plls. also, quicklogic p lls can be cascaded to su pport different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. most importantly, they achieve a very shor t clock-to-out time?generally less than 3 ns. this low clock-to-out time is achieved by th e pll subtracting the clock tree delay through the feedback path, effectively making the clock tree delay zero. figure 3 illustrates a typical quicklogic esp pll. figure 3: pll block f in represents a very stable high-frequency input clock and produces an accurate signal reference. this signal can either bypass the pll entirely, thus entering the cl ock tree directly, or it can pass through the pll itself. within the pll, a voltage-controlled oscillator (vco) is added to the circuit. the external f in signal and the local vco form a control loop. the vco is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in figure 3 ) can compare the two signals. if the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter ( figure 3 ). the charge pump generates an error voltage to bring the vco back into alignment and the loop filter removes any high frequency noise before the error voltage enters the vco. this new vco signal enters the clock tree to drive the chip's circuitry. f out represents the clock signal that emerges from th e output pad (the output signal pllpad_out is explained in table 5 ). this clock signal is meaningful only wh en the pll is configur ed for external use; otherwise, it remains in high z state, as shown in the post-simulation waveform. vco filter fin fout + - 1st quadrant 2nd quadrant 3 rd quadrant 4th quadrant clock tree frequency divide frequency multiply 1 . _ . 2 . _ . 4 . _ . 4 . _ . 2 . _ . 1 . . _ pll bypass www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 6 most quicklogic products contain four plls, one to be used in each quadrant. the pll presented in figure 3 controls the clock tree in the fourth quadrant of its esp. as previously mentioned, quicklogic plls compensate for the additional delay created by the clock tree itself by subtracting the clock tree delay through the feedback path. for more specific information on the phase locked loops, please refer to application note 58 at http://www.quicklogic.com /images/appnote58.pdf . pll modes of operation quicklogic plls have eight modes of operation, base d on the input frequency and desired output frequency? table 4 indicates the features of each mode. table 4: pll mode frequencies pll model output frequency input frequency range a a. the input frequency can range from 12.5 mhz to 500 mhz, whil e output frequency ranges from 25 mhz to 250 mhz. when you add plls to your top-level design, be sure that the pll mode matches your desired input and output frequencies. output frequency range pll_hf b b. hf stands for high frequency and lf stands for low frequency. same as input frequency 66 mhz?150 mhz 66 mhz?150 mhz pll_lf same as input frequency 25 mhz?133 mhz 25 mhz?133 mhz pll_mult2hf 2 input frequency 50 mhz?125 mhz 100 mhz?250 mhz pll_mult2lf 2 input frequency 16 mhz?50 mhz 32 mhz?100 mhz pll_div2hf 1/2 input frequency 100 mhz?250 mhz 50 mhz?125 mhz pll_div2lf 1/2 input frequency 50 mhz?100 mhz 25 mhz?50 mhz pll_mult4 4 input frequency 16 mhz?40 mhz 64 mhz?160 mhz pll_div4 1/4 input frequency 100 mhz?300 mhz 25 mhz?75 mhz ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 7 pll signals table 5 summarizes the key signals in quicklogic?s plls. table 5: pll signals signal name description pllclk_in a a. because pllclk_in and pllrst signals have inpad, and pll pad_out has outpad, you do not have to add additional pads to your design. input clock signal pllrst active high reset if pllrst is asserted, then cl knet_out and pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. onn_offchip pll output this signal selects whether the pll will drive the internal clock network or be used off-chip. this is a static signal, not a dynamic signal. tied to gnd = outgoing signal drives internal gates. tied to vcc = outgoing signal used off-chip. clknet_out out to internal gates this signal bypasses the pll logic before driving the internal gates. note that this signal cannot be used in the same quadrant where the pll signal is used (pllclk_out). pllclk_out out from pll to internal gates this signal can drive the internal gates after going through the pll. for this to work, onn_offchip must be tied to gnd. pllpad_out out to off-chip this outgoing signal is used off-chip. for this to work, onn_offchip signal must be tied to vcc. lock_detect active high lock detection signal note: for simulation purposes, this signal gets asserted after 10 clock cycles. however, it c an take a maximum of 200 clock cycles to sync with the input cloc k upon release of the reset signal. www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 8 joint test access group (jtag) figure 4: jtag block diagram microprocessors and application specific integrated circuits (asics) pose many design challenges, one problem being the accessibility of test points. the joint test access group (jtag) formed in response to this challenge, resulting in ieee standard 1149.1, the standard test access po rt and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run th ree required tests along with several user-defined tests. jtag tests allow users to reduce syst em debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. the 1149.1 standard requires the following three tests: ? extest instruction. the extest instruction performs a pcb interc onnect test. this test places a device into an external boundary test mode, selecting the bounda ry scan register to be connected between the tap's test data in (tdi) and test data out (tdo) pins. boun dary scan cells are preloade d with test patterns (via the sample/preload instruction), and input boundary cells captur e the input data for analysis. ? sample/preload instruction. this instru ction allows a device to remain in its functional mode, while selecting the boundary scan register to be connect ed between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. ? bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypa ss register. the bypass instruction allows users to test a device without passing through other devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device withou t affecting the operation of the device. tck tm s tr s tb rdi tdo in s tr u ction decode & control logic tap controller s t a te m a chine (16 s t a te s ) in s tr u ction regi s ter bo u nd a ry- s c a nregi s ter (d a t a regi s ter) m u x byp ass regi s ter m u x intern a l regi s ter i/o regi s ter s u s er defined d a t a regi s ter ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 9 electrical specifications ac characteristics* *(at v cc = 2.5 v, ta = 25 c, typical corner, speed grade = -7 (k = 1.00)) the ac specifications are provided from table 6 to table 14 . logic cell diagrams and waveforms are provided from figure 5 to figure 1 8 . figure 5: eclipseplus logic cell table 6: logic cells symbol parameter value (ns) min. max. t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output 0.205 1.01 t su setup time: time the synchronous input of the flip flop must be stable before the active clock edge 0.231 - t hl hold time: time the synchronous input of the flip flop must be stable after the active clock edge 0- t co clock to out delay: the amount of time taken by the flip flop to output after the active clock edge. - 0.427 t cwhi clock high time: required minimum time the clock stays high 0.46 - t cwlo clock low time: required minimum time that the clock stays low 0.46 - t set set delay: time between when th e flip flop is ?set? (high) and when the output is c onsequently ?set? (high) -0.585 www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 10 figure 6: logic cell flip-flop figure 7: logic cell flip-flop timings?first waveform t reset reset delay: time between when the flip flop is ?reset? (low) and when the output is consequently ?reset? (low) - 0.658 t sw set width: time that the set signal remains high/low 0.3 - t rw reset width: time that the reset signal remains high/low 0.3 - table 6: logic cells (continued) symbol parameter value (ns) min. max. set d clk reset q s et re s et q clk t cwhi (min) t cwlo (min) t re s et t rw t s et t s w ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 11 figure 8: logic cell flip-flop timings?second waveform figure 9: eclipseplus global clock structure table 7: eclipse global clock tree delays clock segment parameter value (ns) max. rise max. fall t pgck global clock pin delay to quad net 0.990 1.386 t bgck global clock buffer delay (quad net to flip flop) 0.534 1.865 clk d q t s u t hl t co quad net www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 12 figure 10: global clock structure schematic figure 11: ram module table 8: ram cell synchronous write timing symbol parameter value (ns) min. max. t swa wa setup time to wclk: time the wr ite address must be stable before the active edge of the write clock 0.675 ns - t hwa wa hold time to wclk: time the write a ddress must be stable after the active edge of the write clock 0 ns - t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.654 ns - t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns - t swe we setup time to wclk: time the wr ite enable must be stable before the active edge of the write clock 0.276 ns - t hwe we hold time to wclk: time the write enable must be stable after the active edge of the write clock 0 ns - t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd - 2.796 ns programmable clock external clock global clock buffer global clock t pgck t bgck clock select wa wd we wclk re rclk ra rd ram mod ule [9:0] [17:0] [9:0] [17:0] asyncrd ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 1 3 figure 12: ram cell synchronous write timing table 9: ram cell synchronous & asynchronous read timing symbol parameter value (ns) min. max. ram cell synchronous read timing t sra ra setup time to rclk: ti me the read address must be stable before the active edge of the read clock 0.686 ns - t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns - t sre re setup time to wclk: time the read enable must be stable before the active edge of the read clock 0.243 ns - t hre re hold time to wclk: time the read enable must be stable after the active edge of the read clock 0 ns - t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd - 2.225 ns ram cell asynchronous read timing r pdrd ra to rd: time between when the read address is input and when the data is output - 2.405 ns t s wa t s wd t s we t hwa t hwd t hwe t wcrd old d a t a new d a t a wclk wa wd we rd www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 14 figure 13: ram cell synchronous & asynchronous read timing figure 14: eclipseplus cell i/o t s ra t hra rclk ra t s re t hre t rcrd old d a t a new d a t a re rd r pdrd e r q d r q e r q d + - pad output enable regi s ter output regi s ter input regi s ter d ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 15 figure 15: eclipseplus input register cell table 10: input register cell symbol parameter value (ns) min. max. t isu input register setup time: the time the sy nchronous input of the pin must be stable before the active clock edge 3.308 ns 3.526 ns t ihl input register hold time: the time the syn chronous input of the flip-flop must be stable after the active clock edge 0 ns - t ico input register clock-to-out: the time taken by the flip-flop to output after the active clock edge - 0.494 ns t irst input register reset delay: the time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) - 0.464 ns t iesu input register clock enable setup time: the time ?enable? must be stable before the active clock edge 0.830 ns 0.987 ns t ieh input register clock enable hold time: the time ?enable? must be stable after the active clock edge 0 ns - pad t i s u t s id + - q e d r www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 16 figure 16: eclipseplus input register cell timing table 11: standard input delays symbol parameter value (ns) standard input delays to get the total input delay add this delay to t isu min. max. t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications - 0.34 t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications - 0.42 t sid (gtl+) gtl+ input delay: gunning transceiver logic - 0.68 t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v - 0.55 t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v - 0.61 r clk d q i s uihl ico ie s u ieh ir s t e t t t t t t ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 17 figure 17: eclipseplus output register cell table 12: eclipseplus output register cell symbol parameter value output register cell only min. max. t outlh output delay low to high (90% of h) - 0.40 ns t outhl output delay high to low (10% of l) - 0.55 ns t pzh output delay tri-state to high (90% of h) - 2.94 ns t pzl output delay tri-state to low (10% of l) - 2.34 ns t phz output delay high to tri-state - 3.07 ns t plz output delay low to tri-state - 2.53 ns t cop clock-to-out delay (does not include clock tree delays) - 3.15 ns (fast slew) 10.2 ns (slow slew) pad output register www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 1 8 figure 18: eclipseplus output register cell timing note: for tips to minimize ground bounce, refer to application note 66 at http://www.quicklogic.com /images/appnote66.pdf . table 13: output slew rates @ v ccio = 3.3 v fast slew slow slew rising edge 2.8 v/ns 1.0 v/ns falling edge 2.86 v/ns 1.0 v/ns table 14: output slew rates @ v ccio = 2.5 v fast slew slow slew rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns l h l h t outlh t outhl l h z t pzh l h z t pzl l h z t plz l h z t phz ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 19 dc characteristics the dc specifications are provided in table 15 through table 20 . table 15: absolute maximum ratings parameter value parameter value v cc voltage -0.5 v to 3.6 v dc input current 20 ma v ccio voltage -0.5 v to 4.6 v esd pad protection 2000 v inref voltage 2.7 v leaded package storage temperature -65 c to + 150 c input voltage a a. all dedicated inputs including the clk, dedclk, p llin, pllrst, and ioctrl pins, are clamped to the v cc rail, not the v ccio . therefore, these pins can only be driven up to v cc + 0.3 v. these input pins are lvcmos2 compliant only (2.5 v). -0.5 v to v ccio +0.5 v laminate package (bga) storage temperature -55 c to + 125 c latch-up immunity 100 ma table 16: recommended operating range symbol parameter military industrial commercial unit min. max. min. max. min. max. vcc supply voltage 2.3 2.7 2.3 2.7 2.3 2.7 v vccio i/o input tolerance voltage 2.3 3.6 2.3 3.6 2.3 3.6 v tj ambient temperature -55 - -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -4 speed grade 0.42 2.3 0.43 2.16 0.47 2.11 n/a -5 speed grade 0.42 1.92 0.43 1.80 0.46 1.76 n/a -6 speed grade 0.42 1.35 0.43 1.26 0.46 1.23 n/a -7 speed grade 0.42 1.27 0.43 1.19 0.46 1.16 n/a www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 20 note: if plls are not used, the v cc pll and pllrst pins may be grounded to the lower i cc for the device. note: all clk and ioctrl pins are clamped to the v cc rail, not the v ccio . therefore, these pins can only be driven up to v cc + 0.3 v. note: all dedicated inputs including th e clk, dedclk, pllin, pllrst, and ioctrl pins, are clamped to the v cc rail, not the v ccio . therefore, these pins can only be driven up to v cc + 0.3 v. these input pins are lvcmos2 compliant only (2.5 v). table 17: dc characteristics symbol parameter conditions min. max. units i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3-state output leakage current v i = v ccio or gnd -10 10 a c i input capacitance a a. capacitance is sample tested only. clock pins are 12 pf maximum. --8pf i os output short circuit current b b. only one output at a time. duration should not exceed 30 seconds. v o = gnd v o = v cc -15 40 -180 210 ma ma i cc d.c. supply current c c. for -4/-5/-6/-7 commerc ial grade devices only. see table 1 8 for more details on i cc characteristics. v i, v o = v ccio or gnd 0.50 (typ.) 2 ma i ccio d.c. supply current on v ccio - 0 2 ma i ccio (dif) d.c. supply current on v ccio for differential i/o ---ma i ref d.c. supply current on inref - -10 10 a i pd pad pull-down (programmable) v ccio = 3.6 v - 150 a table 18: i cc characteristics characteristic condition temperature commercial industrial military i cc v cc pll = gnd 2 ma (max) 3 ma (max) 5 ma (max) v cc pll = v cc 3.25 ma (max) 5 ma (max) 10 ma (max) table 19: dc input and output levels a a. the data provided in table 19 are jedec and pci specifications. quicklogic devices ei ther meet or exceed these requirements. for data specific to quicklogic i/os, see table 10 through table 20 and figure 14 through figure 20 . inref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lvttl n/a n/a -0.3 0.8 2.0 v ccio + 0.3 0.4 2.4 2.0 -2.0 lv c m o s 2 n/a n/a -0.3 0.7 1.7 v ccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x v ccio 0.5 x v ccio v ccio + 0.5 0.1 x v ccio 0.9 x v ccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 v ccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 1.10 1.90 8 -8 ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 21 i/o characteristics figure 19: iol vs. vol figure 20: ioh vs. voh iol v s vol 0 20 40 60 8 0 100 120 140 160 1 8 0 0.00 0.20 0.40 0.60 0. 8 01.001.201.401.601. 8 0 2.00 2.20 2.40 2.60 2. 8 0 3 .00 su pply volt a ge (v) c u rrent (ma) vccio = 3 .6v vccio = 3 . 3 v vccio = 3 .0v vccio = 2.7v vccio = 2.5v vccio = 2. 3 v -120 -100 - 8 0 -60 -40 -20 0 20 0.00 0.10 0. 3 0 0.50 0.70 0. 9 0 1.10 1. 3 0 1.50 1.70 1. 9 0 2.10 2. 3 0 2.50 2. 70 2. 9 0 3 .00 3 .10 3 . 3 0 3 .50 3 .60 su pply volt a ge (v) c u rrent (ma) vcci/o = 2. 3 v vcci/o = 2.5v vcci/o = 2.7v vcci/o = 3 . 3 v vcci/o = 3 .6v vcci/0 = 3 .0v ioh v s voh www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 22 package thermal characteristics thermal resistance equations: jc = (t j - t c )/p ja = (tj - ta)/p p max = (t jmax - t amax )/ ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power dissipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 150c. to calculate the maximum power dissipation for a device package look up ja from table 21 , pick an appropriate t amax and use: p max = (150oc - t amax )/ ja table 20: max i/o per device /package combination device 20 8 pqfp 2 8 0 lfbga 4 8 4 pbga 516 pbga ql7100 99 163 250 - ql7120 99 163 310 - ql7160 - 163 327 347 ql7180 - 163 327 347 table 21: package thermal characteristics package description ja (oc/w) @ various flow rates (m/sec) jc (oc/w) pin count package type 0 0.5 1 2 516 pbga 20.0 19.0 17.5 16.0 7.0 484 pbga 28.0 26.0 25.0 23.0 9.0 280 lfbga 18.5 17.0 15.5 14.0 7.0 208 pqfp 26.0 24.5 23.0 22.0 11.0 ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 2 3 kv and kt graphs figure 21: voltage factor vs. supply voltage figure 22: temperature factor vs. operating temperature volt a ge f a ctor v s . su pply volt a ge 0. 9 200 0. 9 400 0. 9 600 0. 98 00 1.0000 1.0200 1.0400 1.0600 1.0 8 00 1.1000 2.25 2. 3 2. 3 5 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75 su pply volt a ge (v) kv temper a t u re f a ctor v s .oper a ting temper a t u re 0. 8 5 0. 9 0 0. 9 5 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 8 0 j u nction temper a t u re c kt www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 24 power vs. operating frequency the basic power equation which best mo dels power consumption is given below: p total = 0.350 + f [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] (mw) where: lc is the total number of logic cells in the design ckbf = # of clock buffers clbf = # of column clock buffers ckld = # of loads connected to the column clock buffers ram = # of ram blocks pll = # of plls inp is the number of input pins outp is the number of output pins figure 2 3 exhibits the power consumption in an eclipseplu s device. the chip was filled with (300) 8-bit counters ? approximately 76% logic cell utilization. figure 23: power consumption power v s fre q .(co u nter_ 3 00) 0 0.5 1 1.5 2 2.5 0204060 8 0 100 120 140 fre qu ency (mhz) power (w) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 25 figure 24 illustrates the theoretical wo rst-case scenarios for 50%, 70%, and 90% utilizations of the ql7160/ql7180-516 package. the resources of the device are divided exactly in half; meaning, for 50% utilization, exactly 50% of the i/os, logic cells, ram bl ocks, clock network, etc. are utilized. these situations may never occur in a real design, but they do provide a very rough quantitative measure of power consumption when talking in terms of 50% or 70% utilization of an eclipseplus device. figure 24: power vs. frequency (absolute 50%, 70%, and 90% of the available resources on chip) note: to learn more about power consumption, see quicklogic application note 60 at http://www.quicklogic.com/images/appnote60.pdf . power v s .fre qu ency 0 1 2 3 4 5 6 7 0 50 100 150 200 250 3 00 fre qu ency (mhz) 50 % 70 % 9 0 % power (w) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 26 power-up sequencing figure 25: power-up requirements when powering up a device, the v cc /v ccio rails must take 400 s or long er to reach the maximum value (refer to figure 25 ). note: ramping v cc /v ccio to the maximum voltage faster than 400 s can cause the device to behave improperly. for users with a limited power budget, keep (v ccio -v cc ) max 500 mv when ramping up the power supply. volt a ge v ccio v cc (v ccio -v cc ) max 400 us v cc ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 27 pin descriptions note: all jtag inputs are clamped to the v cc rail, not the v ccio . therefore, these pins can only be driven up to v cc + 0.3 v. these input pins are lvcmos2 compliant only (2.5 v). all jtag outputs are driven by the v cc rail, not v ccio . therefore, these output pins can only drive up to v cc + 0.3 v. these output pins are lvcmos2 compliant only (2.5 v). figure 26: i/o banks with relevant pins table 22: jtag pin descriptions pin function description tdi/rsi test data in for jtag/ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to v cc if unused trstb/rro active low reset for jtag/ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag tdo/rco test data out for jtag/ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization io bank a io bank b v ccio (a) inref(a) ioctrl(a) io(a) v ccio (a) inref(a) ioctrl(a) io(a) io bank c io bank d v ccio (c) inref(c) ioctrl(c) io(c) v ccio (d) inref(d) ioctrl(d) io(d) io bank f io bank e v ccio (f) inref(f) ioctrl(f) io(f) v ccio (e) inref(e) ioctrl(e) io(e) io bank h io bank g (h) inref(h) ioctrl(h) io(h) v ccio v ccio (g) inref(g) ioctrl(g) io(g) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 2 8 table 23: dedicated pin descriptions pin direction function description clk a a. all dedicated inputs including the clk, dedclk, plli n, pllrst, and ioctrl pins, are clamped to the v cc rail, not the v ccio . therefore, these pins can only be driven up to v cc + 0.3 v. these input pins are lvcmos2 compliant only (2.5 v). i global clock network driver low skew global clock. this pin provides access to a dedicated, distributed network capable of driving the clock, set, reset, f1, and a2 inputs to the logic cell, read, and write clocks, read and write enables of the embedded ram blocks, clock of the ecus, and output enables of the i/os. i/o(a) i/o input/output pin the i/o pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-directional pin. the a inside the parenthesis means that the i/o is lo cated in bank a. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. v cc i power supply pin connect to 2.5 v supply v ccio (a) i input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v device or a 2.5 v device. the a inside the parenthesis means that v ccio is located in bank a. every i/o pin in bank a will be tolerant of v ccio input signals and will output v ccio level signals. this pin must be connected to either 3.3 v or v cc . v cc pll b b. all pllout output pi ns are driven by the v cc rail, not the v ccio rail. these output pins are lvcmos2 compliant only (2.5 v). i phase locked loop power supply pin connect to 2.5 v supply. vccpll should be connected to 2.5 v supply if the plls are used. if the plls are not used, v cc pll can be connected to 2.5 v supply or gnd. see table 1 8 for i cc differences when v cc pll is connected to 2.5 v or gnd. gnd i ground pin connect to ground pllin a i pll clock input clock input for pll dedclk a i dedicated clock pin low skew global clock. this pin provides access to a dedicated, distributed clock network capable of driving the clock inputs of all sequential elements of the device (e.g. ram, flip flops). gndpll i ground pin for pll connect to gnd inref(a) i differential reference voltage the inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in table 21 for the appropriate standard. the a inside the parenthesis means that inref is located in bank a. this pin should be tied to gnd if not needed. pllout o pll output pin dedicated pll output pin. otherwise may be left unconnected pllrst a i reset input pin for pll reset input for pll. if plls are not used, pllrst should be connected to the same voltage as v cc pll (e.g., v cc or gnd). ioctrl(a) a i high drive input this pin provides fast reset, set, clock, and enable access to the i/o cell flip-flops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high- drive pin to the internal logic cells. the a inside the parenthesis means that ioctrl is located in bank a. this pin should be tied to gnd or v cc if it is not used. ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 29 recommended unused pin terminat ions for the eclipseplus devices all unused, general purpose i/ o pins can be tied to v cc , gnd, or hiz (high impedance) internally using the configuration editor. this option is given in the botto m-right corner of the placement window. to use the placement editor, choose constraint ? fix placement in the option pull-down menu of spde. the rest of the pins should be terminated at the board level in the manner presented in table 24 . table 24: recommended unused pin terminations signal name recommended termination pllout www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 0 ql7100 ? 20 8 pqfp pinout diagram eclipseplus ql7100-4pq208c ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 1 ql7100 ? 20 8 pqfp pinout table table 25: 208 pqfp pinout table pqfp function pqfp function pqfp function pqfp function pqfp function 1 pllrst(3) 4 3 io(b) 8 5 io(d) 127 clk(5), pllin(3) 169 ioctrl(g) 2 v ccpll (3) 44 v ccio (b) 8 6 v cc 12 8 clk(6) 170 inref(g) 3 gnd 45 io(b) 8 7 io(d) 129 v cc 171 ioctrl(g) 4 gnd 46 v cc 88 io(d) 1 3 0 clk(7) 172 io(g) 5 io(a) 47 io(b) 8 9 v cc 1 3 1 v cc 17 3 io(g) 6 io(a) 4 8 io(b) 90 io(d) 1 3 2 clk(8) 174 io(g) 7 io(a) 49 gnd 91 io(d) 1 33 tms 175 v cc 8 v ccio (a) 50 tdo 92 ioctrl(d) 1 3 4 io(f) 176 io(g) 9 io(a) 51 pllout(1) 9 3 inref(d) 1 3 5 io(f) 177 v ccio (g) 10 io(a) 52 gndpll(2) 94 ioctrl(d) 1 3 6 io(f) 17 8 gnd 11 ioctrl(a) 5 3 gnd 95 io(d) 1 3 7 gnd 179 io(g) 12 v cc 54 v ccpll (2) 96 io(d) 1 38 v ccio (f) 1 8 0 io(g) 1 3 inref(a) 55 pllrst(2) 97 io(d) 1 3 9 io(f) 1 8 1 io(g) 14 ioctrl(a) 56 v cc 9 8 v ccio (d) 140 io(f) 1 8 2 v cc 15 io(a) 57 io(c) 99 io(d) 141 io(f) 1 83 tck 16 io(a) 5 8 gnd 100 io(d) 142 io(f) 1 8 4 v cc 17 io(a) 59 io(c) 101 gnd 14 3 io(f) 1 8 5 io(h) 1 8 io(a) 60 v ccio (c) 102 pllout(0) 144 ioctrl(f) 1 8 6 io(h) 19 v ccio (a) 61 io(c) 10 3 gnd 145 inref(f) 1 8 7 io(h) 20 io(a) 62 io(c) 104 gndpll(1) 146 v cc 1 88 gnd 21 gnd 6 3 io(c) 105 pllrst(1) 147 ioctrl(f) 1 8 9 v ccio (h) 22 io(a) 64 io(c) 106 v ccpll (1) 14 8 io(f) 190 io(h) 2 3 tdi 65 io(c) 107 io(e) 149 io(f) 191 io(h) 24 clk(0) 66 io(c) 10 8 gnd 150 v ccio (f) 192 ioctrl(h) 25 clk(1) 67 ioctrl(c) 109 io(e) 151 io(f) 19 3 io(h) 26 v cc 6 8 inref(c) 110 io(e) 152 io(f) 194 inref(h) 27 clk(2), pllin(2) 69 ioctrl(c) 111 v ccio (e) 15 3 gnd 195 v cc 2 8 clk(3), pllin(1) 70 io(c) 112 io(e) 154 io(f) 196 ioctrl(h) 29 v cc 71 io(c) 11 3 v cc 155 pllout(3) 197 io(h) 3 0 clk(4), dedclk, pllin(0) 72 v ccio (c) 114 io(e) 156 gndpll(0) 19 8 io(h) 3 1 io(b) 7 3 io(c) 115 io(e) 157 gnd 199 io(h) 3 2 io(b) 74 io(c) 116 io(e) 15 8 v ccpll (0) 200 io(h) 33 gnd 75 gnd 117 ioctrl(e) 159 pllrst(0) 201 io(h) 3 4 v ccio (b) 76 v cc 11 8 inref(e) 160 gnd 202 io(h) 3 5 io(b) 77 io(c) 119 ioctrl(e) 161 io(g) 20 3 v ccio (h) 3 6 io(b) 7 8 trstb 120 io(e) 162 v ccio (g) 204 gnd 3 7 io(b) 79 v cc 121 io(e) 16 3 io(g) 205 io(h) 38 io(b) 8 0 io(d) 122 v ccio (e) 164 io(g) 206 pllout(2) 3 9 ioctrl(b) 8 1 io(d) 12 3 gnd 165 v cc 207 gnd 40 inref(b) 8 2 io(d) 124 io(e) 166 io(g) 20 8 gndpll(3) 41 ioctrl(b) 83 gnd 125 io(e) 167 io(g) 42 io(b) 8 4 v ccio (d) 126 io(e) 16 8 io(g) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 2 ql7100 ? 2 8 0 lfbga pinout diagram top bottom eclipseplus ql7100-4pt280c pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 33 ql7100 ? 2 8 0 lfbga pinout table table 26: 280 lfbga pinout table lfbga function lfbga function lfbga function lfbga function lfbga function lfbga function a1 pllout(3) c10 clk(5)/ pllin(3) e19 ioctrl(d) k16 i/o(c) r4 i/o(h) u1 3 i/o(b) a2 gndpll(0) c11 v ccio (e) f1 inref(g) k17 i/o(d) r5 gnd u14 ioctrl(b) a 3 i/o(f) c12 i/o(e) f2 ioctrl(g) k1 8 i/o(c) r6 gnd u15 v ccio (b) a4 i/o(f) c1 3 i/o(e) f 3 i/o(g) k19 trstb r7 v cc u16 i/o(b) a5 i/o(f) c14 i/o(e) f4 i/o(g) l1 i/o(h) r 8 v cc u17 tdo a6 ioctrl(f) c15 v ccio (e) f5 gnd l2 i/o(h) r9 gnd u1 8 pllrst(2) a7 i/o(f) c16 i/o(e) f15 v cc l 3 v ccio (h) r10 gnd u19 i/o(b) a 8 i/o(f) c17 i/o(e) f16 ioctrl(d) l4 i/o(h) r11 v cc v1 pllout(2) a9 i/o(f) c1 8 i/o(e) f17 i/o(d) l5 v cc r12 v cc v2 gndpll(3) a10 clk(7) c19 i/o(e) f1 8 i/o(d) l15 gnd r1 3 v cc v 3 gnd a11 i/o(e) d1 i/o(g) f19 i/o(d) l16 i/o(c) r14 v cc v4 i/o(a) a12 i/o(e) d2 i/o(g) g1 i/o(g) l17 v ccio (c) r15 gnd v5 i/o(a) a1 3 i/o(e) d 3 i/o(f) g2 i/o(g) l1 8 i/o(c) r16 i/o(c) v6 ioctrl(a) a14 ioctrl(e) d4 i/o(f) g 3 ioctrl(g) l19 i/o(c) r17 v ccio (c) v7 i/o(a) a15 i/o(e) d5 i/o(f) g4 i/o(g) m1 i/o(h) r1 8 i/o(c) v 8 i/o(a) a16 i/o(e) d6 i/o(f) g5 v cc m2 i/o(h) r19 i/o(c) v9 i/o(a) a17 i/o(e) d7 i/o(f) g15 v cc m 3 i/o(h) t1 i/o(h) v10 clk(1) a1 8 pllrst(1) d 8 i/o(f) g16 i/o(d) m4 i/o(h) t2 i/o(h) v11 clk(4) dedclk/ pllin(0) a19 gnd d9 clk(8) g17 i/o(d) m5 v cc t 3 i/o(a) v12 i/o(b) b1 pllrst(0) d10 i/o(e) g1 8 i/o(d) m15 v cc t4 i/o(a) v1 3 i/o(b) b2 gnd d11 i/o(e) g19 i/o(d) m16 inref(c) t5 i/o(a) v14 inref(b) b 3 i/o(f) d12 i/o(e) h1 i/o(g) m17 i/o(c) t6 ioctrl(a) v15 i/o(b) b4 i/o(f) d1 3 inref(e) h2 i/o(g) m1 8 i/o(c) t7 i/o(a) v16 i/o(b) b5 i/o(f) d14 i/o(e) h 3 i/o(g) m19 i/o(c) t 8 i/o(a) v17 i/o(b) b6 inref(f) d15 i/o(e) h4 i/o(g) n1 ioctrl(h) t9 i/o(a) v1 8 gndpll(2) b7 i/o(f) d16 i/o(d) h5 v cc n2 i/o(h) t10 i/o(a) v19 gnd b 8 i/o(f) d17 i/o(d) h15 v cc n 3 i/o(h) t11 clk(3)/ pllin(1) w1 gnd b9 tms d1 8 i/o(d) h16 v cc n4 i/o(h) t12 i/o(b) w2 pllrst(3) b10 clk(6) d19 i/o(d) h17 i/o(d) n5 v cc t1 3 i/o(b) w 3 i/o(a) b11 i/o(e) e1 i/o(g) h1 8 i/o(d) n15 v cc t14 i/o(b) w4 i/o(a) b12 i/o(e) e2 i/o(g) h19 i/o(d) n16 i/o(c) t15 i/o(b) w5 i/o(a) b1 3 ioctrl(e) e 3 v ccio (g) j1 i/o(g) n17 i/o(c) t16 i/o(b) w6 i/o(a) b14 i/o(e) e4 i/o(f) j2 i/o(g) n1 8 ioctrl(c) t17 v ccpll (2) w7 i/o(a) b15 i/o(e) e5 gnd j 3 v ccio (g) n19 ioctrl(c) t1 8 i/o(b) w 8 i/o(a) b16 i/o(e) e6 v cc j4 i/o(g) p1 i/o(h) t19 i/o(b) w9 tdi b17 v ccpll (1) e7 v cc j5 gnd p2 i/o(h) u1 i/o(a) w10 clk(2)/ pllin(2) b1 8 gndpll(1) e 8 v cc j15 v cc p 3 ioctrl(h) u2 i/o(a) w11 i/o(b) b19 pllout(0) e9 v cc j16 i/o(c) p4 inref(h) u 3 v ccpll (3) w12 i/o(b) c1 i/o(f) e10 gnd j17 v ccio (d) p5 v cc u4 i/o(a) w1 3 i/o(b) c2 v ccpll (0) e11 gnd j1 8 i/o(d) p15 gnd u5 v ccio (a) w14 ioctrl(b) c 3 i/o(f) e12 v cc j19 i/o(d) p16 i/o(c) u6 inref(a) w15 i/o(b) c4 i/o(f) e1 3 v cc k1 v cc p17 i/o(c) u7 i/o(a) w16 i/o(b) c5 v ccio (f) e14 gnd k2 tck p1 8 i/o(c) u 8 i/o(a) w17 i/o(b) c6 ioctrl(f) e15 gnd k 3 i/o(g) p19 i/o(c) u9 v ccio (a) w1 8 i/o(b) c7 i/o(f) e16 i/o(d) k4 i/o(g) r1 i/o(h) u10 clk(0) w19 pllout(1) c 8 i/o(f) e17 v ccio (d) k5 gnd r2 i/o(h) u11 v ccio (b) c9 v ccio (f) e1 8 inref(d) k15 gnd r 3 v ccio (h) u12 i/o(b) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 4 ql7100 ? 4 8 4 pbga pinout diagram top bottom eclipseplus ql7100-4ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 a b aa pin a1 corner pin a1 ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 5 ql7100 ? 4 8 4 pbga pinout table table 27: 484 pbga pinout table pbga function pbga function pbga function pbga function pbga function pbga function a1 nc c1 nc e1 ioctrl(a) g1 nc j1 i/o(a) l1 clk(4) dedclk/ pllin(0) a2 pllrst(3) c2 i/o(a) e2 i/o(a) g2 nc j2 i/o(a) l2 clk(0) a 3 i/o(a) c 3 v ccpll (3) e 3 i/o(a) g 3 i/o(a) j 3 i/o(a) l 3 clk(2)/ pllin(2) a4 i/o(a) c4 pllout(2) e4 i/o(a) g4 i/o(a) j4 i/o(a) l4 i/o(a) a5 i/o(a) c5 i/o(a) e5 nc g5 i/o(a) j5 i/o(a) l5 i/o(a) a6 nc c6 nc e6 i/o(h) g6 i/o(a) j6 i/o(a) l6 i/o(a) a7 i/o(h) c7 i/o(h) e7 nc g7 gnd j7 i/o(a) l7 gnd a 8 ioctrl(h) c 8 nc e 8 i/o(h) g 8 i/o(h) j 8 v cc l 8 gnd a9 i/o(h) c9 ioctrl(h) e9 i/o(h) g9 i/o(h) j9 gnd l9 gnd a10 nc c10 nc e10 i/o(h) g10 nc j10 v cc l10 gnd a11 nc c11 i/o(h) e11 v cc g11 i/o(g) j11 v cc l11 gnd a12 tck c12 nc e12 i/o(g) g12 gnd j12 gnd l12 gnd a1 3 i/o(g) c1 3 i/o(g) e1 3 i/o(g) g1 3 nc j1 3 v cc l1 3 gnd a14 i/o(g) c14 nc e14 nc g14 nc j14 gnd l14 v cc a15 i/o(g) c15 i/o(g) e15 ioctrl(g) g15 i/o(g) j15 v cc l15 v cc a16 nc c16 i/o(g) e16 i/o(g) g16 gnd j16 i/o(f) l16 clk(6) a17 i/o(g) c17 nc e17 inref(g) g17 v ccio (f) j17 v ccio (f) l17 v ccio (f) a1 8 i/o(g) c1 8 i/o(g) e1 8 nc g1 8 i/o(f) j1 8 i/o(f) l1 8 i/o(f) a19 i/o(f) c19 i/o(f) e19 i/o(f) g19 i/o(f) j19 i/o(f) l19 clk(8) a20 gnd c20 gndpll(0) e20 i/o(f) g20 i/o(f) j20 i/o(f) l20 i/o(f) a21 pllout(3) c21 i/o(f) e21 nc g21 inref(f) j21 i/o(f) l21 nc a22 i/o(f) c22 i/o(f) e22 i/o(f) g22 i/o(f) j22 i/o(f) l22 i/o(f) b1 i/o(a) d1 i/o(a) f1 i/o(a) h1 i/o(a) k1 tdi m1 i/o(b) b2 gnd d2 i/o(a) f2 inref(a) h2 i/o(a) k2 i/o(a) m2 i/o(b) b 3 gndpll(3) d 3 i/o(a) f 3 nc h 3 i/o(a) k 3 i/o(a) m 3 i/o(b) b4 gnd d4 i/o(a) f4 i/o(a) h4 i/o(a) k4 i/o(a) m4 clk(3)/ pllin(1) b5 i/o(a) d5 i/o(a) f5 i/o(a) h5 ioctrl(a) k5 i/o(a) m5 nc b6 i/o(h) d6 i/o(h) f6 v ccio (a) h6 v ccio (a) k6 v ccio (a) m6 v ccio (b) b7 i/o(h) d7 nc f7 v ccio (h) h7 i/o(h) k7 nc m7 clk(1) b 8 inref(h) d 8 i/o(h) f 8 i/o(h) h 8 gnd k 8 v cc m 8 v cc b9 i/o(h) d9 nc f9 v ccio (h) h9 v cc k9 v cc m9 v cc b10 i/o(h) d10 i/o(h) f10 i/o(h) h10 v cc k10 gnd m10 gnd b11 i/o(h) d11 i/o(h) f11 v ccio (h) h11 v cc k11 gnd m11 gnd b12 nc d12 i/o(g) f12 v ccio (g) h12 gnd k12 gnd m12 gnd b1 3 nc d1 3 i/o(g) f1 3 i/o(g) h1 3 v cc k1 3 gnd m1 3 gnd b14 nc d14 i/o(g) f14 v ccio (g) h14 v cc k14 v cc m14 gnd b15 nc d15 ioctrl(g) f15 nc h15 gnd k15 v cc m15 gnd b16 i/o(g) d16 i/o(g) f16 v ccio (g) h16 i/o(f) k16 nc m16 gnd b17 i/o(g) d17 i/o(g) f17 nc h17 i/o(f) k17 i/o(f) m17 i/o(e) b1 8 i/o(g) d1 8 i/o(f) f1 8 i/o(f) h1 8 nc k1 8 i/o(f) m1 8 i/o(e) b19 pllrst(0) d19 v ccpll (0) f19 i/o(f) h19 i/o(f) k19 nc m19 i/o(e) b20 i/o(f) d20 i/o(f) f20 ioctrl(f) h20 i/o(f) k20 i/o(f) m20 clk(7) b21 i/o(f) d21 i/o(f) f21 i/o(f) h21 i/o(f) k21 i/o(f) m21 clk(5)/ pllin(3) b22 i/o(f) d22 i/o(f) f22 ioctrl(f) h22 nc k22 nc m22 tms www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 6 n1 nc p16 i/o(e) t9 nc v2 i/o(b) w17 nc aa10 i/o(c) n2 i/o(b) p17 nc t10 trstb v 3 i/o(b) w1 8 i/o(e) aa11 i/o(c) n 3 i/o(b) p1 8 i/o(e) t11 gnd v4 i/o(b) w19 nc aa12 i/o(d) n4 nc p19 nc t12 nc v5 i/o(b) w20 i/o(e) aa1 3 i/o(d) n5 i/o(b) p20 i/o(e) t1 3 i/o(d) v6 nc w21 nc aa14 i/o(d) n6 nc p21 i/o(e) t14 nc v7 i/o(c) w22 i/o(e) aa15 i/o(d) n7 nc p22 i/o(e) t15 i/o(d) v 8 i/o(c) y1 i/o(b) aa16 nc n 8 v cc r1 i/o(b) t16 gnd v9 nc y2 i/o(b) aa17 nc n9 v cc r2 inref(b) t17 i/o(e) v10 i/o(c) y 3 v ccpll (2) aa1 8 i/o(d) n10 gnd r 3 i/o(b) t1 8 i/o(e) v11 nc y4 i/o(c) aa19 i/o(e) n11 gnd r4 i/o(b) t19 nc v12 v cc y5 i/o(c) aa20 gndpll(1) n12 gnd r5 i/o(b) t20 nc v1 3 nc y6 i/o(c) aa21 i/o(e) n1 3 gnd r6 nc t21 ioctrl(e) v14 i/o(d) y7 i/o(c) aa22 i/o(e) n14 v cc r7 i/o(b) t22 i/o(e) v15 i/o(d) y 8 ioctrl(c) ab1 i/o(b) n15 v cc r 8 gnd u1 ioctrl(b) v16 inref(d) y9 i/o(c) ab2 gndpll(2) n16 i/o(e) r9 v cc u2 i/o(b) v17 i/o(d) y10 i/o(c) ab 3 pllrst(2) n17 v ccio (e) r10 v cc u 3 ioctrl(b) v1 8 i/o(e) y11 i/o(d) ab4 i/o(b) n1 8 i/o(e) r11 gnd u4 i/o(b) v19 i/o(e) y12 nc ab5 i/o(b) n19 i/o(e) r12 v cc u5 i/o(b) v20 i/o(e) y1 3 nc ab6 i/o(c) n20 i/o(e) r1 3 v cc u6 i/o(c) v21 i/o(e) y14 i/o(d) ab7 i/o(c) n21 i/o(e) r14 v cc u7 v ccio (c) v22 i/o(e) y15 ioctrl(d) ab 8 ioctrl(c) n22 i/o(e) r15 gnd u 8 nc w1 i/o(b) y16 i/o(d) ab9 i/o(c) p1 nc r16 i/o(d) u9 v ccio (c) w2 i/o(b) y17 i/o(d) ab10 i/o(c) p2 i/o(b) r17 v ccio (e) u10 i/o(c) w 3 i/o(b) y1 8 i/o(e) ab11 nc p 3 i/o(b) r1 8 i/o(e) u11 v ccio (c) w4 i/o(b) y19 pllout(0) ab12 i/o(d) p4 i/o(b) r19 i/o(e) u12 v ccio (d) w5 i/o(b) y20 pllrst(1) ab1 3 i/o(d) p5 i/o(b) r20 i/o(e) u1 3 i/o(d) w6 i/o(c) y21 i/o(e) ab14 nc p6 v ccio (b) r21 i/o(e) u14 v ccio (d) w7 nc y22 i/o(e) ab15 i/o(d) p7 i/o(b) r22 i/o(e) u15 nc w 8 nc aa1 tdo ab16 ioctrl(d) p 8 v cc t1 i/o(b) u16 v ccio (d) w9 nc aa2 pllout(1) ab17 i/o(d) p9 gnd t2 i/o(b) u17 v ccio (e) w10 nc aa 3 gnd ab1 8 i/o(d) p10 v cc t 3 i/o(b) u1 8 i/o(e) w11 i/o(c) aa4 i/o(b) ab19 i/o(e) p11 gnd t4 i/o(b) u19 i/o(e) w12 nc aa5 i/o(c) ab20 gnd p12 v cc t5 i/o(b) u20 ioctrl(e) w1 3 i/o(d) aa6 i/o(c) ab21 v ccpll (1) p1 3 v cc t6 v ccio (b) u21 nc w14 nc aa7 nc ab22 i/o(e) p14 gnd t7 gnd u22 inref(e) w15 i/o(d) aa 8 inref(c) p15 v cc t 8 i/o(c) v1 i/o(b) w16 nc aa9 nc table 27: 484 pbga pinout table (continued) pbga function pbga function pbga function pbga function pbga function pbga function ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 7 ql7120 ? 20 8 pqfp pinout diagram eclipseplus ql7120-4pq208c www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 38 ql7120 ? 20 8 pqfp pinout table table 28: 208 pqfp pinout table pqfp function pqfp function pqfp function pqfp function pqfp function 1 pllrst(3) 4 3 io(b) 8 5 io(d) 127 clk(5), pllin(3) 169 ioctrl(g) 2 v ccpll (3) 44 v ccio (b) 8 6 v cc 12 8 clk(6) 170 inref(g) 3 gnd 45 io(b) 8 7 io(d) 129 v cc 171 ioctrl(g) 4 gnd 46 v cc 88 io(d) 1 3 0 clk(7) 172 io(g) 5 io(a) 47 io(b) 8 9 v cc 1 3 1 v cc 17 3 io(g) 6 io(a) 4 8 io(b) 90 io(d) 1 3 2 clk(8) 174 io(g) 7 io(a) 49 gnd 91 io(d) 1 33 tms 175 v cc 8 v ccio (a) 50 tdo 92 ioctrl(d) 1 3 4 io(f) 176 io(g) 9 io(a) 51 pllout(1) 9 3 inref(d) 1 3 5 io(f) 177 v ccio (g) 10 io(a) 52 gndpll(2) 94 ioctrl(d) 1 3 6 io(f) 17 8 gnd 11 ioctrl(a) 5 3 gnd 95 io(d) 1 3 7 gnd 179 io(g) 12 v cc 54 v ccpll (2) 96 io(d) 1 38 v ccio (f) 1 8 0 io(g) 1 3 inref(a) 55 pllrst(2) 97 io(d) 1 3 9 io(f) 1 8 1 io(g) 14 ioctrl(a) 56 v cc 9 8 v ccio (d) 140 io(f) 1 8 2 v cc 15 io(a) 57 io(c) 99 io(d) 141 io(f) 1 83 tck 16 io(a) 5 8 gnd 100 io(d) 142 io(f) 1 8 4 v cc 17 io(a) 59 io(c) 101 gnd 14 3 io(f) 1 8 5 io(h) 1 8 io(a) 60 v ccio (c) 102 pllout(0) 144 ioctrl(f) 1 8 6 io(h) 19 v ccio (a) 61 io(c) 10 3 gnd 145 inref(f) 1 8 7 io(h) 20 io(a) 62 io(c) 104 gndpll(1) 146 v cc 1 88 gnd 21 gnd 6 3 io(c) 105 pllrst(1) 147 ioctrl(f) 1 8 9 v ccio (h) 22 io(a) 64 io(c) 106 v ccpll (1) 14 8 io(f) 190 io(h) 2 3 tdi 65 io(c) 107 io(e) 149 io(f) 191 io(h) 24 clk(0) 66 io(c) 10 8 gnd 150 v ccio (f) 192 ioctrl(h) 25 clk(1) 67 ioctrl(c) 109 io(e) 151 io(f) 19 3 io(h) 26 v cc 6 8 inref(c) 110 io(e) 152 io(f) 194 inref(h) 27 clk(2), pllin(2) 69 ioctrl(c) 111 v ccio (e) 15 3 gnd 195 v cc 2 8 clk(3), pllin(1) 70 io(c) 112 io(e) 154 io(f) 196 ioctrl(h) 29 v cc 71 io(c) 11 3 v cc 155 pllout(3) 197 io(h) 3 0 clk(4), dedclk, pllin(0) 72 v ccio (c) 114 io(e) 156 gndpll(0) 19 8 io(h) 3 1 io(b) 7 3 io(c) 115 io(e) 157 gnd 199 io(h) 3 2 io(b) 74 io(c) 116 io(e) 15 8 v ccpll (0) 200 io(h) 33 gnd 75 gnd 117 ioctrl(e) 159 pllrst(0) 201 io(h) 3 4 v ccio (b) 76 v cc 11 8 inref(e) 160 gnd 202 io(h) 3 5 io(b) 77 io(c) 119 ioctrl(e) 161 io(g) 20 3 v ccio (h) 3 6 io(b) 7 8 trstb 120 io(e) 162 v ccio (g) 204 gnd 3 7 io(b) 79 v cc 121 io(e) 16 3 io(g) 205 io(h) 38 io(b) 8 0 io(d) 122 v ccio (e) 164 io(g) 206 pllout(2) 3 9 ioctrl(b) 8 1 io(d) 12 3 gnd 165 v cc 207 gnd 40 inref(b) 8 2 io(d) 124 io(e) 166 io(g) 20 8 gndpll(3) 41 ioctrl(b) 83 gnd 125 io(e) 167 io(g) 42 io(b) 8 4 v ccio (d) 126 io(e) 16 8 io(g) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 3 9 ql7120 ? 2 8 0 pbga pinout diagram top bottom eclipseplus ql7120-4pt280c pin a1 corner www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 40 ql7120 ? 2 8 0 lfbga pinout table table 29: 280 lfbga pinout table lfbga function lfbga function lfbga function lfbga function lfbga function lfbga function a1 pllout(3) c10 clk(5) / pllin(3) e19 ioctrl(d) k16 i/o(c) r4 i/o(h) u1 3 i/o(b) a2 gndpll(0) c11 v ccio (e) f1 inref(g) k17 i/o(d) r5 gnd u14 ioctrl(b) a 3 i/o(f) c12 i/o(e) f2 ioctrl(g) k1 8 i/o(c) r6 gnd u15 v ccio (b) a4 i/o(f) c1 3 i/o(e) f 3 i/o(g) k19 trstb r7 v cc u16 i/o(b) a5 i/o(f) c14 i/o(e) f4 i/o(g) l1 i/o(h) r 8 v cc u17 tdo a6 ioctrl(f) c15 v ccio (e) f5 gnd l2 i/o(h) r9 gnd u1 8 pllrst(2) a7 i/o(f) c16 i/o(e) f15 v cc l 3 v ccio (h) r10 gnd u19 i/o(b) a 8 i/o(f) c17 i/o(e) f16 ioctrl(d) l4 i/o(h) r11 v cc v1 pllout(2) a9 i/o(f) c1 8 i/o(e) f17 i/o(d) l5 v cc r12 v cc v2 gndpll(3) a10 clk(7) c19 i/o(e) f1 8 i/o(d) l15 gnd r1 3 v cc v 3 gnd a11 i/o(e) d1 i/o(g) f19 i/o(d) l16 i/o(c) r14 v cc v4 i/o(a) a12 i/o(e) d2 i/o(g) g1 i/o(g) l17 v ccio (c) r15 gnd v5 i/o(a) a1 3 i/o(e) d 3 i/o(f) g2 i/o(g) l1 8 i/o(c) r16 i/o(c) v6 ioctrl(a) a14 ioctrl(e) d4 i/o(f) g 3 ioctrl(g) l19 i/o(c) r17 v ccio (c) v7 i/o(a) a15 i/o(e) d5 i/o(f) g4 i/o(g) m1 i/o(h) r1 8 i/o(c) v 8 i/o(a) a16 i/o(e) d6 i/o(f) g5 v cc m2 i/o(h) r19 i/o(c) v9 i/o(a) a17 i/o(e) d7 i/o(f) g15 v cc m 3 i/o(h) t1 i/o(h) v10 clk(1) a1 8 pllrst(1) d 8 i/o(f) g16 i/o(d) m4 i/o(h) t2 i/o(h) v11 clk(4) dedclk/ pllin(0) a19 gnd d9 clk(8) g17 i/o(d) m5 v cc t 3 i/o(a) v12 i/o(b) b1 pllrst(0) d10 i/o(e) g1 8 i/o(d) m15 v cc t4 i/o(a) v1 3 i/o(b) b2 gnd d11 i/o(e) g19 i/o(d) m16 inref(c) t5 i/o(a) v14 inref(b) b 3 i/o(f) d12 i/o(e) h1 i/o(g) m17 i/o(c) t6 ioctrl(a) v15 i/o(b) b4 i/o(f) d1 3 inref(e) h2 i/o(g) m1 8 i/o(c) t7 i/o(a) v16 i/o(b) b5 i/o(f) d14 i/o(e) h 3 i/o(g) m19 i/o(c) t 8 i/o(a) v17 i/o(b) b6 inref(f) d15 i/o(e) h4 i/o(g) n1 ioctrl(h) t9 i/o(a) v1 8 gndpll(2) b7 i/o(f) d16 i/o(d) h5 v cc n2 i/o(h) t10 i/o(a) v19 gnd b 8 i/o(f) d17 i/o(d) h15 v cc n 3 i/o(h) t11 clk(3)/ pllin(1) w1 gnd b9 tms d1 8 i/o(d) h16 v cc n4 i/o(h) t12 i/o(b) w2 pllrst(3) b10 clk(6) d19 i/o(d) h17 i/o(d) n5 v cc t1 3 i/o(b) w 3 i/o(a) b11 i/o(e) e1 i/o(g) h1 8 i/o(d) n15 v cc t14 i/o(b) w4 i/o(a) b12 i/o(e) e2 i/o(g) h19 i/o(d) n16 i/o(c) t15 i/o(b) w5 i/o(a) b1 3 ioctrl(e) e 3 v ccio (g) j1 i/o(g) n17 i/o(c) t16 i/o(b) w6 i/o(a) b14 i/o(e) e4 i/o(f) j2 i/o(g) n1 8 ioctrl(c) t17 v ccpll (2) w7 i/o(a) b15 i/o(e) e5 gnd j 3 v ccio (g) n19 ioctrl(c) t1 8 i/o(b) w 8 i/o(a) b16 i/o(e) e6 v cc j4 i/o(g) p1 i/o(h) t19 i/o(b) w9 tdi b17 v ccpll (1) e7 v cc j5 gnd p2 i/o(h) u1 i/o(a) w10 clk(2)/ pllin(2) b1 8 gndpll(1) e 8 v cc j15 v cc p 3 ioctrl(h) u2 i/o(a) w11 i/o(b) b19 pllout(0) e9 v cc j16 i/o(c) p4 inref(h) u 3 v ccpll (3) w12 i/o(b) c1 i/o(f) e10 gnd j17 v ccio (d) p5 v cc u4 i/o(a) w1 3 i/o(b) c2 v ccpll (0) e11 gnd j1 8 i/o(d) p15 gnd u5 v ccio (a) w14 ioctrl(b) c 3 i/o(f) e12 v cc j19 i/o(d) p16 i/o(c) u6 inref(a) w15 i/o(b) c4 i/o(f) e1 3 v cc k1 v cc p17 i/o(c) u7 i/o(a) w16 i/o(b) c5 v ccio (f) e14 gnd k2 tck p1 8 i/o(c) u 8 i/o(a) w17 i/o(b) c6 ioctrl(f) e15 gnd k 3 i/o(g) p19 i/o(c) u9 v ccio (a) w1 8 i/o(b) c7 i/o(f) e16 i/o(d) k4 i/o(g) r1 i/o(h) u10 clk(0) w19 pllout(1) c 8 i/o(f) e17 v ccio (d) k5 gnd r2 i/o(h) u11 v ccio (b) c9 v ccio (f) e1 8 inref(d) k15 gnd r 3 v ccio (h) u12 i/o(b) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 41 ql7120 ? 4 8 4 pbga pinout diagram top bottom eclipseplus ql7120-4ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 a b aa pin a1 corner pin a1 www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 42 ql7120 ? 4 8 4 pbga pinout table table 30: 484 pbga pinout table pbga function pbga function pbga function pbga function pbga function pbga function a1 i/o(a) c1 i/o(a) e1 ioctrl(a) g1 i/o(a) j1 i/o(a) l1 clk(4) dedclk/ pllin(0) a2 pllrst(3) c2 i/o(a) e2 i/o(a) g2 i/o(a) j2 i/o(a) l2 clk(0) a 3 i/o(a) c 3 v ccpll (3) e 3 i/o(a) g 3 i/o(a) j 3 i/o(a) l 3 clk(2)/ pllin(2) a4 i/o(a) c4 pllout(2) e4 i/o(a) g4 i/o(a) j4 i/o(a) l4 i/o(a) a5 i/o(a) c5 i/o(a) e5 i/o(a) g5 i/o(a) j5 i/o(a) l5 i/o(a) a6 i/o(h) c6 i/o(h) e6 i/o(h) g6 i/o(a) j6 i/o(a) l6 i/o(a) a7 i/o(h) c7 i/o(h) e7 n/c g7 gnd j7 i/o(a) l7 gnd a 8 ioctrl(h) c 8 i/o(h) e 8 i/o(h) g 8 i/o(h) j 8 v cc l 8 gnd a9 i/o(h) c9 ioctrl(h) e9 i/o(h) g9 i/o(h) j9 gnd l9 gnd a10 n/c c10 i/o(h) e10 i/o(h) g10 i/o(h) j10 v cc l10 gnd a11 n/c c11 i/o(h) e11 v cc g11 i/o(g) j11 v cc l11 gnd a12 tck c12 i/o(h) e12 i/o(g) g12 gnd j12 gnd l12 gnd a1 3 i/o(g) c1 3 i/o(g) e1 3 i/o(g) g1 3 i/o(g) j1 3 v cc l1 3 gnd a14 i/o(g) c14 i/o(g) e14 i/o(g) g14 i/o(g) j14 gnd l14 v cc a15 i/o(g) c15 i/o(g) e15 ioctrl(g) g15 i/o(g) j15 v cc l15 v cc a16 i/o(g) c16 i/o(g) e16 i/o(g) g16 gnd j16 i/o(f) l16 clk(6) a17 i/o(g) c17 i/o(g) e17 inref(g) g17 v ccio (f) j17 v ccio (f) l17 v ccio (f) a1 8 i/o(g) c1 8 i/o(g) e1 8 i/o(g) g1 8 i/o(f) j1 8 i/o(f) l1 8 i/o(f) a19 i/o(f) c19 i/o(f) e19 i/o(f) g19 i/o(f) j19 i/o(f) l19 clk(8) a20 gnd c20 gndpll(0) e20 i/o(f) g20 i/o(f) j20 i/o(f) l20 i/o(f) a21 pllout(3) c21 i/o(f) e21 i/o(f) g21 inref(f) j21 i/o(f) l21 i/o(f) a22 i/o(f) c22 i/o(f) e22 i/o(f) g22 i/o(f) j22 i/o(f) l22 i/o(f) b1 i/o(a) d1 i/o(a) f1 i/o(a) h1 i/o(a) k1 tdi m1 i/o(b) b2 gnd d2 i/o(a) f2 inref(a) h2 i/o(a) k2 i/o(a) m2 i/o(b) b 3 gndpll(3) d 3 i/o(a) f 3 i/o(a) h 3 i/o(a) k 3 i/o(a) m 3 i/o(b) b4 gnd d4 i/o(a) f4 i/o(a) h4 i/o(a) k4 i/o(a) m4 clk(3)/ pllin(1) b5 i/o(a) d5 i/o(a) f5 i/o(a) h5 ioctrl(a) k5 i/o(a) m5 i/o(b) b6 i/o(h) d6 i/o(h) f6 v ccio (a) h6 v ccio (a) k6 v ccio (a) m6 v ccio (b) b7 i/o(h) d7 i/o(h) f7 v ccio (h) h7 i/o(h) k7 i/o(a) m7 clk(1) b 8 inref(h) d 8 i/o(h) f 8 i/o(h) h 8 gnd k 8 v cc m 8 v cc b9 i/o(h) d9 i/o(h) f9 v ccio (h) h9 v cc k9 v cc m9 v cc b10 i/o(h) d10 i/o(h) f10 i/o(h) h10 v cc k10 gnd m10 gnd b11 i/o(h) d11 i/o(h) f11 v ccio (h) h11 v cc k11 gnd m11 gnd b12 n/c d12 i/o(g) f12 v ccio (g) h12 gnd k12 gnd m12 gnd b1 3 n/c d1 3 i/o(g) f1 3 i/o(g) h1 3 v cc k1 3 gnd m1 3 gnd b14 n/c d14 i/o(g) f14 v ccio (g) h14 v cc k14 v cc m14 gnd b15 i/o(g) d15 ioctrl(g) f15 n/c h15 gnd k15 v cc m15 gnd b16 i/o(g) d16 i/o(g) f16 v ccio (g) h16 i/o(f) k16 i/o(f) m16 gnd b17 i/o(g) d17 i/o(g) f17 n/c h17 i/o(f) k17 i/o(f) m17 i/o(e) b1 8 i/o(g) d1 8 i/o(f) f1 8 i/o(f) h1 8 i/o(f) k1 8 i/o(f) m1 8 i/o(e) b19 pllrst(0) d19 v ccpll (0) f19 i/o(f) h19 i/o(f) k19 i/o(f) m19 i/o(e) b20 i/o(f) d20 i/o(f) f20 ioctrl(f) h20 i/o(f) k20 i/o(f) m20 clk(7) b21 i/o(f) d21 i/o(f) f21 i/o(f) h21 i/o(f) k21 i/o(f) m21 clk(5)/pllin (3) b22 i/o(f) d22 i/o(f) f22 ioctrl(f) h22 i/o(f) k22 i/o(f) m22 tms ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 4 3 n1 i/o(b) p16 i/o(e) t9 n/c v2 i/o(b) w17 i/o(d) aa10 i/o(c) n2 i/o(b) p17 i/o(e) t10 trstb v 3 i/o(b) w1 8 i/o(e) aa11 i/o(c) n 3 i/o(b) p1 8 i/o(e) t11 gnd v4 i/o(b) w19 i/o(e) aa12 i/o(d) n4 i/o(b) p19 i/o(e) t12 n/c v5 i/o(b) w20 i/o(e) aa1 3 i/o(d) n5 i/o(b) p20 i/o(e) t1 3 i/o(d) v6 i/o(c) w21 i/o(e) aa14 i/o(d) n6 i/o(b) p21 i/o(e) t14 n/c v7 i/o(c) w22 i/o(e) aa15 i/o(d) n7 i/o(b) p22 i/o(e) t15 i/o(d) v 8 i/o(c) y1 i/o(b) aa16 i/o(d) n 8 v cc r1 i/o(b) t16 gnd v9 n/c y2 i/o(b) aa17 i/o(d) n9 v cc r2 inref(b) t17 i/o(e) v10 i/o(c) y 3 v ccpll (2) aa1 8 i/o(d) n10 gnd r 3 i/o(b) t1 8 i/o(e) v11 i/o(c) y4 i/o(c) aa19 i/o(e) n11 gnd r4 i/o(b) t19 i/o(e) v12 v cc y5 i/o(c) aa20 gndpll(1) n12 gnd r5 i/o(b) t20 i/o(e) v1 3 n/c y6 i/o(c) aa21 i/o(e) n1 3 gnd r6 i/o(b) t21 ioctrl(e) v14 i/o(d) y7 i/o(c) aa22 i/o(e) n14 v cc r7 i/o(b) t22 i/o(e) v15 i/o(d) y 8 ioctrl(c) ab1 i/o(b) n15 v cc r 8 gnd u1 ioctrl(b) v16 inref(d) y9 i/o(c) ab2 gndpll(2) n16 i/o(e) r9 v cc u2 i/o(b) v17 i/o(d) y10 i/o(c) ab 3 pllrst(2) n17 v ccio (e) r10 v cc u 3 ioctrl(b) v1 8 i/o(e) y11 i/o(d) ab4 i/o(b) n1 8 i/o(e) r11 gnd u4 i/o(b) v19 i/o(e) y12 i/o(d) ab5 i/o(b) n19 i/o(e) r12 v cc u5 i/o(b) v20 i/o(e) y1 3 i/o(d) ab6 i/o(c) n20 i/o(e) r1 3 v cc u6 i/o(c) v21 i/o(e) y14 i/o(d) ab7 i/o(c) n21 i/o(e) r14 v cc u7 v ccio (c) v22 i/o(e) y15 ioctrl(d) ab 8 ioctrl(c) n22 i/o(e) r15 gnd u 8 n/c w1 i/o(b) y16 i/o(d) ab9 i/o(c) p1 i/o(b) r16 i/o(d) u9 v ccio (c) w2 i/o(b) y17 i/o(d) ab10 i/o(c) p2 i/o(b) r17 v ccio (e) u10 i/o(c) w 3 i/o(b) y1 8 i/o(e) ab11 i/o(c) p 3 i/o(b) r1 8 i/o(e) u11 v ccio (c) w4 i/o(b) y19 pllout(0) ab12 i/o(d) p4 i/o(b) r19 i/o(e) u12 v ccio (d) w5 i/o(b) y20 pllrst(1) ab1 3 i/o(d) p5 i/o(b) r20 i/o(e) u1 3 i/o(d) w6 i/o(c) y21 i/o(e) ab14 i/o(d) p6 v ccio (b) r21 i/o(e) u14 v ccio (d) w7 n/c y22 i/o(e) ab15 i/o(d) p7 i/o(b) r22 i/o(e) u15 n/c w 8 i/o(c) aa1 tdo ab16 ioctrl(d) p 8 v cc t1 i/o(b) u16 v ccio (d) w9 i/o(c) aa2 pllout(1) ab17 i/o(d) p9 gnd t2 i/o(b) u17 v ccio (e) w10 i/o(c) aa 3 gnd ab1 8 i/o(d) p10 v cc t 3 i/o(b) u1 8 i/o(e) w11 i/o(c) aa4 i/o(b) ab19 i/o(e) p11 gnd t4 i/o(b) u19 i/o(e) w12 i/o(d) aa5 i/o(c) ab20 gnd p12 v cc t5 i/o(b) u20 ioctrl(e) w1 3 i/o(d) aa6 i/o(c) ab21 v ccpll (1) p1 3 v cc t6 v ccio (b) u21 i/o(e) w14 i/o(d) aa7 i/o(c) ab22 i/o(e) p14 gnd t7 gnd u22 inref(e) w15 i/o(d) aa 8 inref(c) p15 v cc t 8 i/o(c) v1 i/o(b) w16 n/c aa9 i/o(c) table 30: 484 pbga pinout table (continued) pbga function pbga function pbga function pbga function pbga function pbga function www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 44 ql7160 ? 2 8 0 lfbga pinout diagram top bottom eclipseplus ql7160-4pt280c pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 45 ql7160 ? 2 8 0 lfbga pinout table table 31: 280 lfbga pinout table lfbga function lfbga function lfbga function lfbga function lfbga function lfbga function a1 pllout(3) c10 clk(5)/ pllin(3) e19 ioctrl(d) k16 i/o(c) r4 i/o(h) u1 3 i/o(b) a2 gndpll(0) c11 v ccio (e) f1 inref(g) k17 i/o(d) r5 gnd u14 ioctrl(b) a 3 i/o(f) c12 i/o(e) f2 ioctrl(g) k1 8 i/o(c) r6 gnd u15 v ccio (b) a4 i/o(f) c1 3 i/o(e) f 3 i/o(g) k19 trstb r7 v cc u16 i/o(b) a5 i/o(f) c14 i/o(e) f4 i/o(g) l1 i/o(h) r 8 v cc u17 tdo a6 ioctrl(f) c15 v ccio (e) f5 gnd l2 i/o(h) r9 gnd u1 8 pllrst(2) a7 i/o(f) c16 i/o(e) f15 v cc l 3 v ccio (h) r10 gnd u19 i/o(b) a 8 i/o(f) c17 i/o(e) f16 ioctrl(d) l4 i/o(h) r11 v cc v1 pllout(2) a9 i/o(f) c1 8 i/o(e) f17 i/o(d) l5 v cc r12 v cc v2 gndpll(3) a10 clk(7) c19 i/o(e) f1 8 i/o(d) l15 gnd r1 3 v cc v 3 gnd a11 i/o(e) d1 i/o(g) f19 i/o(d) l16 i/o(c) r14 v cc v4 i/o(a) a12 i/o(e) d2 i/o(g) g1 i/o(g) l17 v ccio (c) r15 gnd v5 i/o(a) a1 3 i/o(e) d 3 i/o(f) g2 i/o(g) l1 8 i/o(c) r16 i/o(c) v6 ioctrl(a) a14 ioctrl(e) d4 i/o(f) g 3 ioctrl(g) l19 i/o(c) r17 v ccio (c) v7 i/o(a) a15 i/o(e) d5 i/o(f) g4 i/o(g) m1 i/o(h) r1 8 i/o(c) v 8 i/o(a) a16 i/o(e) d6 i/o(f) g5 v cc m2 i/o(h) r19 i/o(c) v9 i/o(a) a17 i/o(e) d7 i/o(f) g15 v cc m 3 i/o(h) t1 i/o(h) v10 clk(1) a1 8 pllrst(1) d 8 i/o(f) g16 i/o(d) m4 i/o(h) t2 i/o(h) v11 clk(4)/ dedclk/ pllin(0) a19 gnd d9 clk(8) g17 i/o(d) m5 v cc t 3 i/o(a) v12 i/o(b) b1 pllrst(0) d10 i/o(e) g1 8 i/o(d) m15 v cc t4 i/o(a) v1 3 i/o(b) b2 gnd d11 i/o(e) g19 i/o(d) m16 inref(c) t5 i/o(a) v14 inref(b) b 3 i/o(f) d12 i/o(e) h1 i/o(g) m17 i/o(c) t6 ioctrl(a) v15 i/o(b) b4 i/o(f) d1 3 inref(e) h2 i/o(g) m1 8 i/o(c) t7 i/o(a) v16 i/o(b) b5 i/o(f) d14 i/o(e) h 3 i/o(g) m19 i/o(c) t 8 i/o(a) v17 i/o(b) b6 inref(f) d15 i/o(e) h4 i/o(g) n1 ioctrl(h) t9 i/o(a) v1 8 gndpll(2) b7 i/o(f) d16 i/o(d) h5 v cc n2 i/o(h) t10 i/o(a) v19 gnd b 8 i/o(f) d17 i/o(d) h15 v cc n 3 i/o(h) t11 clk(3)/ pllin(1) w1 gnd b9 tms d1 8 i/o(d) h16 v cc n4 i/o(h) t12 i/o(b) w2 pllrst(3) b10 clk(6) d19 i/o(d) h17 i/o(d) n5 v cc t1 3 i/o(b) w 3 i/o(a) b11 i/o(e) e1 i/o(g) h1 8 i/o(d) n15 v cc t14 i/o(b) w4 i/o(a) b12 i/o(e) e2 i/o(g) h19 i/o(d) n16 i/o(c) t15 i/o(b) w5 i/o(a) b1 3 ioctrl(e) e 3 v ccio (g) j1 i/o(g) n17 i/o(c) t16 i/o(b) w6 i/o(a) b14 i/o(e) e4 i/o(f) j2 i/o(g) n1 8 ioctrl(c) t17 v ccpll (2) w7 i/o(a) b15 i/o(e) e5 gnd j 3 v ccio (g) n19 ioctrl(c) t1 8 i/o(b) w 8 i/o(a) b16 i/o(e) e6 v cc j4 i/o(g) p1 i/o(h) t19 i/o(b) w9 tdi b17 v ccpll (1) e7 v cc j5 gnd p2 i/o(h) u1 i/o(a) w10 clk(2)/ pllin(2) b1 8 gndpll(1) e 8 v cc j15 v cc p 3 ioctrl(h) u2 i/o(a) w11 i/o(b) b19 pllout(0) e9 v cc j16 i/o(c) p4 inref(h) u 3 v ccpll (3) w12 i/o(b) c1 i/o(f) e10 gnd j17 v ccio (d) p5 v cc u4 i/o(a) w1 3 i/o(b) c2 v ccpll (0) e11 gnd j1 8 i/o(d) p15 gnd u5 v ccio (a) w14 ioctrl(b) c 3 i/o(f) e12 v cc j19 i/o(d) p16 i/o(c) u6 inref(a) w15 i/o(b) c4 i/o(f) e1 3 v cc k1 v cc p17 i/o(c) u7 i/o(a) w16 i/o(b) c5 v ccio (f) e14 gnd k2 tck p1 8 i/o(c) u 8 i/o(a) w17 i/o(b) c6 ioctrl(f) e15 gnd k 3 i/o(g) p19 i/o(c) u9 v ccio (a) w1 8 i/o(b) c7 i/o(f) e16 i/o(d) k4 i/o(g) r1 i/o(h) u10 clk(0) w19 pllout(1) c 8 i/o(f) e17 v ccio (d) k5 gnd r2 i/o(h) u11 v ccio (b) c9 v ccio (f) e1 8 inref(d) k15 gnd r 3 v ccio (h) u12 i/o(b) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 46 ql7160 ? 4 8 4 pbga pinout diagram top bottom eclipseplus ql7160-4ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 a b aa pin a1 corner pin a1 ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 47 ql7160 ? 4 8 4 pbga pinout table table 32: 484 pbga pinout table pbga function pbga function pbga function pbga function pbga function pbga function a1 i/o(a) c1 i/o(a) e1 ioctrl(a) g1 i/o(a) j1 i/o(a) l1 clk(4)/ dedclk/ pllin(0) a2 pllrst(3) c2 i/o(a) e2 i/o(a) g2 i/o(a) j2 i/o(a) l2 clk(0) a 3 i/o(a) c 3 v ccpll (3) e 3 i/o(a) g 3 i/o(a) j 3 i/o(a) l 3 clk(2)/ pllin(2) a4 i/o(a) c4 pllout(2) e4 i/o(a) g4 i/o(a) j4 i/o(a) l4 i/o(a) a5 i/o(a) c5 i/o(a) e5 i/o(a) g5 i/o(a) j5 i/o(a) l5 i/o(a) a6 i/o(h) c6 i/o(h) e6 i/o(h) g6 i/o(a) j6 i/o(a) l6 i/o(a) a7 i/o(h) c7 i/o(h) e7 i/o(h) g7 gnd j7 i/o(a) l7 gnd a 8 ioctrl(h) c 8 i/o(h) e 8 i/o(h) g 8 i/o(h) j 8 v cc l 8 gnd a9 i/o(h) c9 ioctrl(h) e9 i/o(h) g9 i/o(h) j9 gnd l9 gnd a10 i/o(h) c10 i/o(h) e10 i/o(h) g10 i/o(h) j10 v cc l10 gnd a11 i/o(h) c11 i/o(h) e11 v cc g11 i/o(g) j11 v cc l11 gnd a12 tck c12 i/o(h) e12 i/o(g) g12 gnd j12 gnd l12 gnd a1 3 i/o(g) c1 3 i/o(g) e1 3 i/o(g) g1 3 i/o(g) j1 3 v cc l1 3 gnd a14 i/o(g) c14 i/o(g) e14 i/o(g) g14 i/o(g) j14 gnd l14 v cc a15 i/o(g) c15 i/o(g) e15 ioctrl(g) g15 i/o(g) j15 v cc l15 v cc a16 i/o(g) c16 i/o(g) e16 i/o(g) g16 gnd j16 i/o(f) l16 clk(6) a17 i/o(g) c17 i/o(g) e17 inref(g) g17 v ccio (f) j17 v ccio (f) l17 v ccio (f) a1 8 i/o(g) c1 8 i/o(g) e1 8 i/o(g) g1 8 i/o(f) j1 8 i/o(f) l1 8 i/o(f) a19 i/o(f) c19 i/o(f) e19 i/o(f) g19 i/o(f) j19 i/o(f) l19 clk(8) a20 gnd c20 gndpll(0) e20 i/o(f) g20 i/o(f) j20 i/o(f) l20 i/o(f) a21 pllout(3) c21 i/o(f) e21 i/o(f) g21 inref(f) j21 i/o(f) l21 i/o(f) a22 i/o(f) c22 i/o(f) e22 i/o(f) g22 i/o(f) j22 i/o(f) l22 i/o(f) b1 i/o(a) d1 i/o(a) f1 i/o(a) h1 i/o(a) k1 tdi m1 i/o(b) b2 gnd d2 i/o(a) f2 inref(a) h2 i/o(a) k2 i/o(a) m2 i/o(b) b 3 gndpll(3) d 3 i/o(a) f 3 i/o(a) h 3 i/o(a) k 3 i/o(a) m 3 i/o(b) b4 gnd d4 i/o(a) f4 i/o(a) h4 i/o(a) k4 i/o(a) m4 clk(3)/ pllin(1) b5 i/o(a) d5 i/o(a) f5 i/o(a) h5 ioctrl(a) k5 i/o(a) m5 i/o(b) b6 i/o(h) d6 i/o(h) f6 v ccio (a) h6 v ccio (a) k6 v ccio (a) m6 v ccio (b) b7 i/o(h) d7 i/o(h) f7 v ccio (h) h7 i/o(h) k7 i/o(a) m7 clk(1) b 8 inref(h) d 8 i/o(h) f 8 i/o(h) h 8 gnd k 8 v cc m 8 v cc b9 i/o(h) d9 i/o(h) f9 v ccio (h) h9 v cc k9 v cc m9 v cc b10 i/o(h) d10 i/o(h) f10 i/o(h) h10 v cc k10 gnd m10 gnd b11 i/o(h) d11 i/o(h) f11 v ccio (h) h11 v cc k11 gnd m11 gnd b12 i/o(g) d12 i/o(g) f12 v ccio (g) h12 gnd k12 gnd m12 gnd b1 3 i/o(g) d1 3 i/o(g) f1 3 i/o(g) h1 3 v cc k1 3 gnd m1 3 gnd b14 i/o(g) d14 i/o(g) f14 v ccio (g) h14 v cc k14 v cc m14 gnd b15 i/o(g) d15 ioctrl(g) f15 i/o(g) h15 gnd k15 v cc m15 gnd b16 i/o(g) d16 i/o(g) f16 v ccio (g) h16 i/o(f) k16 i/o(f) m16 gnd b17 i/o(g) d17 i/o(g) f17 i/o(g) h17 i/o(f) k17 i/o(f) m17 i/o(e) b1 8 i/o(g) d1 8 i/o(f) f1 8 i/o(f) h1 8 i/o(f) k1 8 i/o(f) m1 8 i/o(e) b19 pllrst(0) d19 v ccpll (0) f19 i/o(f) h19 i/o(f) k19 i/o(f) m19 i/o(e) b20 i/o(f) d20 i/o(f) f20 ioctrl(f) h20 i/o(f) k20 i/o(f) m20 clk(7) b21 i/o(f) d21 i/o(f) f21 i/o(f) h21 i/o(f) k21 i/o(f) m21 clk(5)/ pllin(3) b22 i/o(f) d22 i/o(f) f22 ioctrl(f) h22 i/o(f) k22 i/o(f) m22 tms www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 4 8 n1 i/o(b) p16 i/o(e) t9 i/o(c) v2 i/o(b) w17 i/o(d) aa10 i/o(c) n2 i/o(b) p17 i/o(e) t10 trstb v 3 i/o(b) w1 8 i/o(e) aa11 i/o(c) n 3 i/o(b) p1 8 i/o(e) t11 gnd v4 i/o(b) w19 i/o(e) aa12 i/o(d) n4 i/o(b) p19 i/o(e) t12 i/o(c) v5 i/o(b) w20 i/o(e) aa1 3 i/o(d) n5 i/o(b) p20 i/o(e) t1 3 i/o(d) v6 i/o(c) w21 i/o(e) aa14 i/o(d) n6 i/o(b) p21 i/o(e) t14 i/o(d) v7 i/o(c) w22 i/o(e) aa15 i/o(d) n7 i/o(b) p22 i/o(e) t15 i/o(d) v 8 i/o(c) y1 i/o(b) aa16 i/o(d) n 8 v cc r1 i/o(b) t16 gnd v9 i/o(c) y2 i/o(b) aa17 i/o(d) n9 v cc r2 inref(b) t17 i/o(e) v10 i/o(c) y 3 v ccpll (2) aa1 8 i/o(d) n10 gnd r 3 i/o(b) t1 8 i/o(e) v11 i/o(c) y4 i/o(c) aa19 i/o(e) n11 gnd r4 i/o(b) t19 i/o(e) v12 v cc y5 i/o(c) aa20 gndpll(1) n12 gnd r5 i/o(b) t20 i/o(e) v1 3 i/o(d) y6 i/o(c) aa21 i/o(e) n1 3 gnd r6 i/o(b) t21 ioctrl(e) v14 i/o(d) y7 i/o(c) aa22 i/o(e) n14 v cc r7 i/o(b) t22 i/o(e) v15 i/o(d) y 8 ioctrl(c) ab1 i/o(b) n15 v cc r 8 gnd u1 ioctrl(b) v16 inref(d) y9 i/o(c) ab2 gndpll(2) n16 i/o(e) r9 v cc u2 i/o(b) v17 i/o(d) y10 i/o(c) ab 3 pllrst(2) n17 v ccio (e) r10 v cc u 3 ioctrl(b) v1 8 i/o(e) y11 i/o(d) ab4 i/o(b) n1 8 i/o(e) r11 gnd u4 i/o(b) v19 i/o(e) y12 i/o(d) ab5 i/o(b) n19 i/o(e) r12 v cc u5 i/o(b) v20 i/o(e) y1 3 i/o(d) ab6 i/o(c) n20 i/o(e) r1 3 v cc u6 i/o(c) v21 i/o(e) y14 i/o(d) ab7 i/o(c) n21 i/o(e) r14 v cc u7 v ccio (c) v22 i/o(e) y15 ioctrl(d) ab 8 ioctrl(c) n22 i/o(e) r15 gnd u 8 i/o(c) w1 i/o(b) y16 i/o(d) ab9 i/o(c) p1 i/o(b) r16 i/o(d) u9 v ccio (c) w2 i/o(b) y17 i/o(d) ab10 i/o(c) p2 i/o(b) r17 v ccio (e) u10 i/o(c) w 3 i/o(b) y1 8 i/o(e) ab11 i/o(c) p 3 i/o(b) r1 8 i/o(e) u11 v ccio (c) w4 i/o(b) y19 pllout(0) ab12 i/o(d) p4 i/o(b) r19 i/o(e) u12 v ccio (d) w5 i/o(b) y20 pllrst(1) ab1 3 i/o(d) p5 i/o(b) r20 i/o(e) u1 3 i/o(d) w6 i/o(c) y21 i/o(e) ab14 i/o(d) p6 v ccio (b) r21 i/o(e) u14 v ccio (d) w7 i/o(c) y22 i/o(e) ab15 i/o(d) p7 i/o(b) r22 i/o(e) u15 i/o(d) w 8 i/o(c) aa1 tdo ab16 ioctrl(d) p 8 v cc t1 i/o(b) u16 v ccio (d) w9 i/o(c) aa2 pllout(1) ab17 i/o(d) p9 gnd t2 i/o(b) u17 v ccio (e) w10 i/o(c) aa 3 gnd ab1 8 i/o(d) p10 v cc t 3 i/o(b) u1 8 i/o(e) w11 i/o(c) aa4 i/o(b) ab19 i/o(e) p11 gnd t4 i/o(b) u19 i/o(e) w12 i/o(d) aa5 i/o(c) ab20 gnd p12 v cc t5 i/o(b) u20 ioctrl(e) w1 3 i/o(d) aa6 i/o(c) ab21 v ccpll (1) p1 3 v cc t6 v ccio (b) u21 i/o(e) w14 i/o(d) aa7 i/o(c) ab22 i/o(e) p14 gnd t7 gnd u22 inref(e) w15 i/o(d) aa 8 inref(c) p15 v cc t 8 i/o(c) v1 i/o(b) w16 i/o(d) aa9 i/o(c) table 32: 484 pbga pinout table (continued) pbga function pbga function pbga function pbga function pbga function pbga function ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 49 ql7160 ? 516 pbga pinout diagram top bottom eclipseplus ql7160-4pb516c pin a1 corner www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 50 ql7160 ? 516 pbga pinout table table 33: 516 pbga pinout table pbga function pbga function pbga function pbga function pbga function pbga function a1 gnd b24 i/o(e) d21 i/o(e) f1 8 v ccio (e) k5 i/o(g) n6 gnd a2 i/o(f) b25 i/o(e) d22 i/o(e) f19 v cc k6 gnd n11 gnd a 3 i/o(f) b26 pllout(0) d2 3 v ccpll (1) f20 v ccio (e) k21 gnd n12 gnd a4 i/o(f) c1 i/o(f) d24 i/o(e) f21 gnd k22 i/o(d) n1 3 gnd a5 i/o(f) c2 i/o(f) d25 i/o(e) f22 i/o(e) k2 3 i/o(d) n14 gnd a6 i/o(f) c 3 i/o(f) d26 i/o(d) f2 3 i/o(d) k24 i/o(d) n15 gnd a7 ioctrl(f) c4 pllout(3) e1 i/o(g) f24 i/o(d) k25 i/o(d) n16 gnd a 8 i/o(f) c5 i/o(f) e2 i/o(g) f25 i/o(d) k26 i/o(d) n21 gnd a9 i/o(f) c6 i/o(f) e 3 i/o(g) f26 i/o(d) l1 i/o(g) n22 i/o(d) a10 i/o(f) c7 i/o(f) e4 v ccpll (0) g1 i/o(g) l2 i/o(g) n2 3 i/o(d) a11 i/o(f) c 8 inref(f) e5 i/o(f) g2 inref(g) l 3 i/o(g) n24 i/o(d) a12 i/o(f) c9 i/o(f) e6 i/o(f) g 3 i/o(g) l4 i/o(g) n25 i/o(d) a1 3 i/o(e) c10 i/o(f) e7 i/o(f) g4 i/o(g) l5 v cc n26 i/o(d) a14 i/o(e) c11 i/o(f) e 8 v cc g5 i/o(g) l6 v cc p1 i/o(h) a15 i/o(e) c12 i/o(f) e9 i/o(f) g6 v ccio (g) l11 gnd p2 i/o(h) a16 i/o(e) c1 3 clk(7) e10 i/o(f) g21 v ccio (d) l12 gnd p 3 i/o(h) a17 i/o(e) c14 i/o(e) e11 i/o(f) g22 i/o(d) l1 3 gnd p4 v cc a1 8 ioctrl(e) c15 i/o(e) e12 v cc g2 3 i/o(d) l14 gnd p5 i/o(h) a19 ioctrl(e) c16 i/o(e) e1 3 i/o(f) g24 i/o(d) l15 gnd p6 v ccio (h) a20 i/o(e) c17 i/o(e) e14 i/o(f) g25 i/o(d) l16 gnd p11 gnd a21 i/o(e) c1 8 i/o(e) e15 i/o(e) g26 inref(d) l21 v cc p12 gnd a22 i/o(e) c19 i/o(e) e16 v cc h1 i/o(g) l22 i/o(d) p1 3 gnd a2 3 i/o(e) c20 i/o(e) e17 clk(6) h2 i/o(g) l2 3 i/o(d) p14 gnd a24 i/o(e) c21 i/o(e) e1 8 i/o(e) h 3 ioctrl(g) l24 i/o(d) p15 gnd a25 pllrst(1) c22 i/o(e) e19 i/o(e) h4 i/o(g) l25 i/o(d) p16 gnd a26 gnd c2 3 i/o(e) e20 i/o(e) h5 i/o(g) l26 i/o(d) p21 v ccio (c) b1 i/o(f) c24 i/o(e) e21 i/o(e) h6 v cc m1 i/o(g) p22 i/o(c) b2 pllrst(0) c25 i/o(e) e22 i/o(e) h21 v cc m2 i/o(g) p2 3 v cc b 3 i/o(f) c26 i/o(e) e2 3 gndpll(1) h22 v cc m 3 i/o(g) p24 i/o(c) b4 i/o(f) d1 i/o(g) e24 i/o(e) h2 3 i/o(d) m4 i/o(g) p25 i/o(c) b5 i/o(f) d2 i/o(g) e25 i/o(d) h24 ioctrl(d) m5 i/o(g) p26 trstb b6 i/o(f) d 3 i/o(f) e26 i/o(d) h25 ioctrl(d) m6 v ccio (g) r1 i/o(h) b7 ioctrl(f) d4 i/o(f) f1 ioctrl(g) h26 i/o(d) m11 gnd r2 i/o(h) b 8 i/o(f) d5 gndpll(0) f2 i/o(g) j1 i/o(g) m12 gnd r 3 i/o(h) b9 i/o(f) d6 i/o(f) f 3 i/o(g) j2 i/o(g) m1 3 gnd r4 i/o(h) b10 i/o(f) d7 i/o(f) f4 i/o(g) j 3 i/o(g) m14 gnd r5 v cc b11 i/o(f) d 8 i/o(f) f5 i/o(f) j4 i/o(g) m15 gnd r6 v cc b12 i/o(f) d9 i/o(f) f6 gnd j5 i/o(g) m16 gnd r11 gnd b1 3 clk(5)/ pllin(3) d10 i/o(f) f7 v ccio (f) j6 v ccio (g) m21 v ccio (d) r12 gnd b14 i/o(e) d11 i/o(f) f 8 v cc j21 v ccio (d) m22 v cc r1 3 gnd b15 i/o(e) d12 i/o(f) f9 v ccio (f) j22 i/o(d) m2 3 i/o(d) r14 gnd b16 i/o(e) d1 3 tms f10 gnd j2 3 i/o(d) m24 i/o(d) r15 gnd b17 i/o(e) d14 i/o(e) f11 v cc j24 i/o(d) m25 i/o(d) r16 gnd b1 8 inref(e) d15 i/o(e) f12 v ccio (f) j25 i/o(d) m26 i/o(d) r21 v cc b19 i/o(e) d16 i/o(f) f1 3 gnd j26 i/o(d) n1 tck r22 i/o(c) b20 i/o(e) d17 i/o(e) f14 v ccio (e) k1 i/o(g) n2 i/o(h) r2 3 i/o(c) b21 i/o(e) d1 8 i/o(f) f15 v cc k2 i/o(g) n 3 i/o(g) r24 i/o(c) b22 i/o(e) d19 clk(8) f16 v cc k 3 i/o(g) n4 i/o(g) r25 i/o(c) b2 3 i/o(e) d20 i/o(e) f17 gnd k4 i/o(g) n5 i/o(g) r26 i/o(c) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 51 t1 i/o(h) v22 i/o(c) aa9 v ccio (a) ab20 i/o(b) ad5 i/o(a) ae16 i/o(b) t2 i/o(h) v2 3 i/o(c) aa10 gnd ab21 i/o(b) ad6 i/o(a) ae17 i/o(b) t 3 i/o(h) v24 ioctrl(c) aa11 v cc ab22 gndpll(2) ad7 i/o(a) ae1 8 i/o(b) t4 i/o(h) v25 i/o(c) aa12 v ccio (a) ab2 3 i/o(b) ad 8 ioctrl(a) ae19 i/o(b) t5 i/o(h) v26 i/o(c) aa1 3 gnd ab24 i/o(c) ad9 i/o(a) ae20 i/o(b) t6 v cc w1 inref(h) aa14 v ccio (b) ab25 i/o(c) ad10 i/o(a) ae21 i/o(b) t11 gnd w2 i/o(h) aa15 v cc ab26 i/o(c) ad11 i/o(a) ae22 i/o(b) t12 gnd w 3 i/o(h) aa16 v cc ac1 i/o(a) ad12 tdi ae2 3 i/o(b) t1 3 gnd w4 i/o(h) aa17 gnd ac2 i/o(a) ad1 3 clk(4) dedclk/ pllin(0) ae24 i/o(b) t14 gnd w5 v cc aa1 8 v ccio (b) ac 3 i/o(a) ad14 i/o(a) ae25 pllrst(2) t15 gnd w6 v cc aa19 v cc ac4 i/o(a) ad15 i/o(b) ae26 i/o(b) t16 gnd w21 v cc aa20 v ccio (b) ac5 i/o(a) ad16 i/o(b) af1 i/o(a) t21 v cc w22 i/o(c) aa21 gnd ac6 i/o(a) ad17 i/o(b) af2 i/o(a) t22 v cc w2 3 i/o(c) aa22 v ccpll (2) ac7 i/o(a) ad1 8 inref(b) af 3 i/o(a) t2 3 i/o(c) w24 i/o(c) aa2 3 i/o(c) ac 8 i/o(a) ad19 i/o(b) af4 i/o(a) t24 i/o(c) w25 inref(c) aa24 i/o(c) ac9 i/o(a) ad20 i/o(b) af5 i/o(a) t25 i/o(c) w26 i/o(c) aa25 i/o(c) ac10 i/o(a) ad21 i/o(b) af6 ioctrl(a) t26 i/o(c) y1 i/o(h) aa26 i/o(c) ac11 i/o(a) ad22 i/o(b) af7 i/o(a) u1 i/o(h) y2 i/o(h) ab1 i/o(h) ac12 i/o(a) ad2 3 i/o(b) af 8 i/o(a) u2 i/o(h) y 3 i/o(h) ab2 i/o(h) ac1 3 i/o(a) ad24 gnd af9 i/o(a) u 3 i/o(h) y4 i/o(h) ab 3 i/o(a) ac14 clk(1) ad25 i/o(b) af10 i/o(a) u4 i/o(h) y5 i/o(h) ab4 gndpll(3) ac15 i/o(b) ad26 i/o(b) af11 i/o(a) u5 i/o(h) y6 v ccio (h) ab5 v ccpll (3) ac16 i/o(b) ae1 gnd af12 clk(2)/p llin(2) u6 gnd y21 v ccio (c) ab6 i/o(a) ac17 i/o(b) ae2 gnd af1 3 i/o(b) u21 gnd y22 i/o(c) ab7 i/o(a) ac1 8 i/o(b) ae 3 i/o(a) af14 i/o(b) u22 i/o(c) y2 3 i/o(c) ab 8 i/o(a) ac19 i/o(b) ae4 i/o(a) af15 i/o(b) u2 3 i/o(c) y24 i/o(c) ab9 i/o(a) ac20 i/o(b) ae5 i/o(a) af16 i/o(b) u24 i/o(c) y25 i/o(c) ab10 i/o(a) ac21 i/o(b) ae6 i/o(a) af17 i/o(b) u25 i/o(c) y26 ioctrl(c) ab11 v cc ac22 tdo ae7 inref(a) af1 8 i/o(b) u26 i/o(c) aa1 i/o(h) ab12 i/o(a) ac2 3 pllout(1) ae 8 i/o(a) af19 ioctrl(b) v1 i/o(h) aa2 i/o(h) ab1 3 i/o(a) ac24 i/o(b) ae9 i/o(a) af20 ioctrl(b) v2 ioctrl(h) aa 3 i/o(h) ab14 clk(3)/ pllin(1) ac25 i/o(b) ae10 i/o(a) af21 i/o(b) v 3 ioctrl(h) aa4 i/o(a) ab15 v cc ac26 i/o(c) ae11 i/o(a) af22 i/o(b) v4 i/o(h) aa5 i/o(a) ab16 i/o(b) ad1 i/o(a) ae12 clk(0) af2 3 i/o(b) v5 i/o(h) aa6 gnd ab17 i/o(b) ad2 pllout(2) ae1 3 i/o(b) af24 i/o(b) v6 v ccio (h) aa7 v ccio (a) ab1 8 i/o(b) ad 3 pllrst(3) ae14 i/o(b) af25 i/o(b) v21 v ccio (c) aa 8 v cc ab19 v cc ad4 i/o(a) ae15 i/o(b) af26 i/o(b) table 33: 516 pbga pinout table (continued) pbga function pbga function pbga function pbga function pbga function pbga function www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 52 ql71 8 0 ? 2 8 0 lfbga pinout diagram top bottom eclipseplus ql7180-4pt280c pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 5 3 ql71 8 0 ? 2 8 0 lfbga pinout table table 34: 280 lfbga pinout table lfbga function lfbga function lfbga function lfbga function lfbga function lfbga function a1 pllout(3) c10 clk(5)/ pllin(3) e19 ioctrl(d) k16 i/o(c) r4 i/o(h) u1 3 i/o(b) a2 gndpll(0) c11 v ccio (e) f1 inref(g) k17 i/o(d) r5 gnd u14 ioctrl(b) a 3 i/o(f) c12 i/o(e) f2 ioctrl(g) k1 8 i/o(c) r6 gnd u15 v ccio (b) a4 i/o(f) c1 3 i/o(e) f 3 i/o(g) k19 trstb r7 v cc u16 i/o(b) a5 i/o(f) c14 i/o(e) f4 i/o(g) l1 i/o(h) r 8 v cc u17 tdo a6 ioctrl(f) c15 v ccio (e) f5 gnd l2 i/o(h) r9 gnd u1 8 pllrst(2) a7 i/o(f) c16 i/o(e) f15 v cc l 3 v ccio (h) r10 gnd u19 i/o(b) a 8 i/o(f) c17 i/o(e) f16 ioctrl(d) l4 i/o(h) r11 v cc v1 pllout(2) a9 i/o(f) c1 8 i/o(e) f17 i/o(d) l5 v cc r12 v cc v2 gndpll(3) a10 clk(7) c19 i/o(e) f1 8 i/o(d) l15 gnd r1 3 v cc v 3 gnd a11 i/o(e) d1 i/o(g) f19 i/o(d) l16 i/o(c) r14 v cc v4 i/o(a) a12 i/o(e) d2 i/o(g) g1 i/o(g) l17 v ccio (c) r15 gnd v5 i/o(a) a1 3 i/o(e) d 3 i/o(f) g2 i/o(g) l1 8 i/o(c) r16 i/o(c) v6 ioctrl(a) a14 ioctrl(e) d4 i/o(f) g 3 ioctrl(g) l19 i/o(c) r17 v ccio (c) v7 i/o(a) a15 i/o(e) d5 i/o(f) g4 i/o(g) m1 i/o(h) r1 8 i/o(c) v 8 i/o(a) a16 i/o(e) d6 i/o(f) g5 v cc m2 i/o(h) r19 i/o(c) v9 i/o(a) a17 i/o(e) d7 i/o(f) g15 v cc m 3 i/o(h) t1 i/o(h) v10 clk(1) a1 8 pllrst(1) d 8 i/o(f) g16 i/o(d) m4 i/o(h) t2 i/o(h) v11 clk(4)/ dedclk/ pllin(0) a19 gnd d9 clk(8) g17 i/o(d) m5 v cc t 3 i/o(a) v12 i/o(b) b1 pllrst(0) d10 i/o(e) g1 8 i/o(d) m15 v cc t4 i/o(a) v1 3 i/o(b) b2 gnd d11 i/o(e) g19 i/o(d) m16 inref(c) t5 i/o(a) v14 inref(b) b 3 i/o(f) d12 i/o(e) h1 i/o(g) m17 i/o(c) t6 ioctrl(a) v15 i/o(b) b4 i/o(f) d1 3 inref(e) h2 i/o(g) m1 8 i/o(c) t7 i/o(a) v16 i/o(b) b5 i/o(f) d14 i/o(e) h 3 i/o(g) m19 i/o(c) t 8 i/o(a) v17 i/o(b) b6 inref(f) d15 i/o(e) h4 i/o(g) n1 ioctrl(h) t9 i/o(a) v1 8 gndpll(2) b7 i/o(f) d16 i/o(d) h5 v cc n2 i/o(h) t10 i/o(a) v19 gnd b 8 i/o(f) d17 i/o(d) h15 v cc n 3 i/o(h) t11 clk(3)/ pllin(1) w1 gnd b9 tms d1 8 i/o(d) h16 v cc n4 i/o(h) t12 i/o(b) w2 pllrst(3) b10 clk(6) d19 i/o(d) h17 i/o(d) n5 v cc t1 3 i/o(b) w 3 i/o(a) b11 i/o(e) e1 i/o(g) h1 8 i/o(d) n15 v cc t14 i/o(b) w4 i/o(a) b12 i/o(e) e2 i/o(g) h19 i/o(d) n16 i/o(c) t15 i/o(b) w5 i/o(a) b1 3 ioctrl(e) e 3 v ccio (g) j1 i/o(g) n17 i/o(c) t16 i/o(b) w6 i/o(a) b14 i/o(e) e4 i/o(f) j2 i/o(g) n1 8 ioctrl(c) t17 v cc pll(2) w7 i/o(a) b15 i/o(e) e5 gnd j 3 v ccio (g) n19 ioctrl(c) t1 8 i/o(b) w 8 i/o(a) b16 i/o(e) e6 v cc j4 i/o(g) p1 i/o(h) t19 i/o(b) w9 tdi b17 v cc pll(1) e7 v cc j5 gnd p2 i/o(h) u1 i/o(a) w10 clk(2)/ pllin(2) b1 8 gndpll(1) e 8 v cc j15 v cc p 3 ioctrl(h) u2 i/o(a) w11 i/o(b) b19 pllout(0) e9 v cc j16 i/o(c) p4 inref(h) u 3 v cc pll(3) w12 i/o(b) c1 i/o(f) e10 gnd j17 v ccio (d) p5 v cc u4 i/o(a) w1 3 i/o(b) c2 v cc pll(0) e11 gnd j1 8 i/o(d) p15 gnd u5 v ccio (a) w14 ioctrl(b) c 3 i/o(f) e12 v cc j19 i/o(d) p16 i/o(c) u6 inref(a) w15 i/o(b) c4 i/o(f) e1 3 v cc k1 v cc p17 i/o(c) u7 i/o(a) w16 i/o(b) c5 v ccio (f) e14 gnd k2 tck p1 8 i/o(c) u 8 i/o(a) w17 i/o(b) c6 ioctrl(f) e15 gnd k 3 i/o(g) p19 i/o(c) u9 v ccio (a) w1 8 i/o(b) c7 i/o(f) e16 i/o(d) k4 i/o(g) r1 i/o(h) u10 clk(0) w19 pllout(1) c 8 i/o(f) e17 v ccio (d) k5 gnd r2 i/o(h) u11 v ccio (b) c9 v ccio (f) e1 8 inref(d) k15 gnd r 3 v ccio (h) u12 i/o(b) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 54 ql71 8 0 ? 4 8 4 pbga pinout diagram top bottom eclipseplus ql7180-4ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 a b aa pin a1 corner pin a1 ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 55 ql71 8 0 ? 4 8 4 pbga pinout table table 35: 484 pbga pinout table pbga function pbga function pbga function pbga function pbga function pbga function a1 i/o(a) c1 i/o(a) e1 ioctrl(a) g1 i/o(a) j1 i/o(a) l1 clk(4) dedclk/ pllin(0) a2 pllrst(3) c2 i/o(a) e2 i/o(a) g2 i/o(a) j2 i/o(a) l2 clk(0) a 3 i/o(a) c 3 v cc pll(3) e 3 i/o(a) g 3 i/o(a) j 3 i/o(a) l 3 clk(2)/pllin(2) a4 i/o(a) c4 pllout(2) e4 i/o(a) g4 i/o(a) j4 i/o(a) l4 i/o(a) a5 i/o(a) c5 i/o(a) e5 i/o(a) g5 i/o(a) j5 i/o(a) l5 i/o(a) a6 i/o(h) c6 i/o(h) e6 i/o(h) g6 i/o(a) j6 i/o(a) l6 i/o(a) a7 i/o(h) c7 i/o(h) e7 i/o(h) g7 gnd j7 i/o(a) l7 gnd a 8 ioctrl(h) c 8 i/o(h) e 8 i/o(h) g 8 i/o(h) j 8 v cc l 8 gnd a9 i/o(h) c9 ioctrl(h) e9 i/o(h) g9 i/o(h) j9 gnd l9 gnd a10 i/o(h) c10 i/o(h) e10 i/o(h) g10 i/o(h) j10 v cc l10 gnd a11 i/o(h) c11 i/o(h) e11 v cc g11 i/o(g) j11 v cc l11 gnd a12 tck c12 i/o(h) e12 i/o(g) g12 gnd j12 gnd l12 gnd a1 3 i/o(g) c1 3 i/o(g) e1 3 i/o(g) g1 3 i/o(g) j1 3 v cc l1 3 gnd a14 i/o(g) c14 i/o(g) e14 i/o(g) g14 i/o(g) j14 gnd l14 v cc a15 i/o(g) c15 i/o(g) e15 ioctrl(g) g15 i/o(g) j15 v cc l15 v cc a16 i/o(g) c16 i/o(g) e16 i/o(g) g16 gnd j16 i/o(f) l16 clk(6) a17 i/o(g) c17 i/o(g) e17 inref(g) g17 v ccio (f) j17 v ccio (f) l17 v ccio (f) a1 8 i/o(g) c1 8 i/o(g) e1 8 i/o(g) g1 8 i/o(f) j1 8 i/o(f) l1 8 i/o(f) a19 i/o(f) c19 i/o(f) e19 i/o(f) g19 i/o(f) j19 i/o(f) l19 clk(8) a20 gnd c20 gndpll(0) e20 i/o(f) g20 i/o(f) j20 i/o(f) l20 i/o(f) a21 pllout(3) c21 i/o(f) e21 i/o(f) g21 inref(f) j21 i/o(f) l21 i/o(f) a22 i/o(f) c22 i/o(f) e22 i/o(f) g22 i/o(f) j22 i/o(f) l22 i/o(f) b1 i/o(a) d1 i/o(a) f1 i/o(a) h1 i/o(a) k1 tdi m1 i/o(b) b2 gnd d2 i/o(a) f2 inref(a) h2 i/o(a) k2 i/o(a) m2 i/o(b) b 3 gndpll(3) d 3 i/o(a) f 3 i/o(a) h 3 i/o(a) k 3 i/o(a) m 3 i/o(b) b4 gnd d4 i/o(a) f4 i/o(a) h4 i/o(a) k4 i/o(a) m4 clk(3)/pllin(1) b5 i/o(a) d5 i/o(a) f5 i/o(a) h5 ioctrl(a) k5 i/o(a) m5 i/o(b) b6 i/o(h) d6 i/o(h) f6 v ccio (a) h6 v ccio (a) k6 v ccio (a) m6 v ccio (b) b7 i/o(h) d7 i/o(h) f7 v ccio (h) h7 i/o(h) k7 i/o(a) m7 clk(1) b 8 inref(h) d 8 i/o(h) f 8 i/o(h) h 8 gnd k 8 v cc m 8 v cc b9 i/o(h) d9 i/o(h) f9 v ccio (h) h9 v cc k9 v cc m9 v cc b10 i/o(h) d10 i/o(h) f10 i/o(h) h10 v cc k10 gnd m10 gnd b11 i/o(h) d11 i/o(h) f11 v ccio (h) h11 v cc k11 gnd m11 gnd b12 i/o(g) d12 i/o(g) f12 v ccio (g) h12 gnd k12 gnd m12 gnd b1 3 i/o(g) d1 3 i/o(g) f1 3 i/o(g) h1 3 v cc k1 3 gnd m1 3 gnd b14 i/o(g) d14 i/o(g) f14 v ccio (g) h14 v cc k14 v cc m14 gnd b15 i/o(g) d15 ioctrl(g) f15 i/o(g) h15 gnd k15 v cc m15 gnd b16 i/o(g) d16 i/o(g) f16 v ccio (g) h16 i/o(f) k16 i/o(f) m16 gnd b17 i/o(g) d17 i/o(g) f17 i/o(g) h17 i/o(f) k17 i/o(f) m17 i/o(e) b1 8 i/o(g) d1 8 i/o(f) f1 8 i/o(f) h1 8 i/o(f) k1 8 i/o(f) m1 8 i/o(e) b19 pllrst(0) d19 v cc pll(0) f19 i/o(f) h19 i/o(f) k19 i/o(f) m19 i/o(e) b20 i/o(f) d20 i/o(f) f20 ioctrl(f) h20 i/o(f) k20 i/o(f) m20 clk(7) b21 i/o(f) d21 i/o(f) f21 i/o(f) h21 i/o(f) k21 i/o(f) m21 clk(5)/pllin(3) b22 i/o(f) d22 i/o(f) f22 ioctrl(f) h22 i/o(f) k22 i/o(f) m22 tms www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 56 n1 i/o(b) p16 i/o(e) t9 i/o(c) v2 i/o(b) w17 i/o(d) aa10 i/o(c) n2 i/o(b) p17 i/o(e) t10 trstb v 3 i/o(b) w1 8 i/o(e) aa11 i/o(c) n 3 i/o(b) p1 8 i/o(e) t11 gnd v4 i/o(b) w19 i/o(e) aa12 i/o(d) n4 i/o(b) p19 i/o(e) t12 i/o(c) v5 i/o(b) w20 i/o(e) aa1 3 i/o(d) n5 i/o(b) p20 i/o(e) t1 3 i/o(d) v6 i/o(c) w21 i/o(e) aa14 i/o(d) n6 i/o(b) p21 i/o(e) t14 i/o(d) v7 i/o(c) w22 i/o(e) aa15 i/o(d) n7 i/o(b) p22 i/o(e) t15 i/o(d) v 8 i/o(c) y1 i/o(b) aa16 i/o(d) n 8 v cc r1 i/o(b) t16 gnd v9 i/o(c) y2 i/o(b) aa17 i/o(d) n9 v cc r2 inref(b) t17 i/o(e) v10 i/o(c) y 3 v cc pll(2) aa1 8 i/o(d) n10 gnd r 3 i/o(b) t1 8 i/o(e) v11 i/o(c) y4 i/o(c) aa19 i/o(e) n11 gnd r4 i/o(b) t19 i/o(e) v12 v cc y5 i/o(c) aa20 gndpll(1) n12 gnd r5 i/o(b) t20 i/o(e) v1 3 i/o(d) y6 i/o(c) aa21 i/o(e) n1 3 gnd r6 i/o(b) t21 ioctrl(e) v14 i/o(d) y7 i/o(c) aa22 i/o(e) n14 v cc r7 i/o(b) t22 i/o(e) v15 i/o(d) y 8 ioctrl(c) ab1 i/o(b) n15 v cc r 8 gnd u1 ioctrl(b) v16 inref(d) y9 i/o(c) ab2 gndpll(2) n16 i/o(e) r9 v cc u2 i/o(b) v17 i/o(d) y10 i/o(c) ab 3 pllrst(2) n17 v ccio (e) r10 v cc u 3 ioctrl(b) v1 8 i/o(e) y11 i/o(d) ab4 i/o(b) n1 8 i/o(e) r11 gnd u4 i/o(b) v19 i/o(e) y12 i/o(d) ab5 i/o(b) n19 i/o(e) r12 v cc u5 i/o(b) v20 i/o(e) y1 3 i/o(d) ab6 i/o(c) n20 i/o(e) r1 3 v cc u6 i/o(c) v21 i/o(e) y14 i/o(d) ab7 i/o(c) n21 i/o(e) r14 v cc u7 v ccio (c) v22 i/o(e) y15 ioctrl(d) ab 8 ioctrl(c) n22 i/o(e) r15 gnd u 8 i/o(c) w1 i/o(b) y16 i/o(d) ab9 i/o(c) p1 i/o(b) r16 i/o(d) u9 v ccio (c) w2 i/o(b) y17 i/o(d) ab10 i/o(c) p2 i/o(b) r17 v ccio (e) u10 i/o(c) w 3 i/o(b) y1 8 i/o(e) ab11 i/o(c) p 3 i/o(b) r1 8 i/o(e) u11 v ccio (c) w4 i/o(b) y19 pllout(0) ab12 i/o(d) p4 i/o(b) r19 i/o(e) u12 v ccio (d) w5 i/o(b) y20 pllrst(1) ab1 3 i/o(d) p5 i/o(b) r20 i/o(e) u1 3 i/o(d) w6 i/o(c) y21 i/o(e) ab14 i/o(d) p6 v ccio (b) r21 i/o(e) u14 v ccio (d) w7 i/o(c) y22 i/o(e) ab15 i/o(d) p7 i/o(b) r22 i/o(e) u15 i/o(d) w 8 i/o(c) aa1 tdo ab16 ioctrl(d) p 8 v cc t1 i/o(b) u16 v ccio (d) w9 i/o(c) aa2 pllout(1) ab17 i/o(d) p9 gnd t2 i/o(b) u17 v ccio (e) w10 i/o(c) aa 3 gnd ab1 8 i/o(d) p10 v cc t 3 i/o(b) u1 8 i/o(e) w11 i/o(c) aa4 i/o(b) ab19 i/o(e) p11 gnd t4 i/o(b) u19 i/o(e) w12 i/o(d) aa5 i/o(c) ab20 gnd p12 v cc t5 i/o(b) u20 ioctrl(e) w1 3 i/o(d) aa6 i/o(c) ab21 v cc pll(1) p1 3 v cc t6 v ccio (b) u21 i/o(e) w14 i/o(d) aa7 i/o(c) ab22 i/o(e) p14 gnd t7 gnd u22 inref(e) w15 i/o(d) aa 8 inref(c) p15 v cc t 8 i/o(c) v1 i/o(b) w16 i/o(d) aa9 i/o(c) table 35: 484 pbga pinout table (continued) pbga function pbga function pbga function pbga function pbga function pbga function ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 57 ql71 8 0 ? 516 pbga pinout diagram top bottom eclipseplus ql7180-4pb516c pin a1 corner www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 5 8 ql71 8 0 ? 516 pbga pinout table table 36: 516 pbga pinout table pbga function pbga function pbga function pbga function pbga function pbga function a1 gnd b24 i/o(e) d21 i/o(e) f1 8 v ccio (e) k5 i/o(g) n6 gnd a2 i/o(f) b25 i/o(e) d22 i/o(e) f19 v cc k6 gnd n11 gnd a 3 i/o(f) b26 pllout(0) d2 3 v cc pll(1) f20 v ccio (e) k21 gnd n12 gnd a4 i/o(f) c1 i/o(f) d24 i/o(e) f21 gnd k22 i/o(d) n1 3 gnd a5 i/o(f) c2 i/o(f) d25 i/o(e) f22 i/o(e) k2 3 i/o(d) n14 gnd a6 i/o(f) c 3 i/o(f) d26 i/o(d) f2 3 i/o(d) k24 i/o(d) n15 gnd a7 ioctrl(f) c4 pllout(3) e1 i/o(g) f24 i/o(d) k25 i/o(d) n16 gnd a 8 i/o(f) c5 i/o(f) e2 i/o(g) f25 i/o(d) k26 i/o(d) n21 gnd a9 i/o(f) c6 i/o(f) e 3 i/o(g) f26 i/o(d) l1 i/o(g) n22 i/o(d) a10 i/o(f) c7 i/o(f) e4 v cc pll(0) g1 i/o(g) l2 i/o(g) n2 3 i/o(d) a11 i/o(f) c 8 inref(f) e5 i/o(f) g2 inref(g) l 3 i/o(g) n24 i/o(d) a12 i/o(f) c9 i/o(f) e6 i/o(f) g 3 i/o(g) l4 i/o(g) n25 i/o(d) a1 3 i/o(e) c10 i/o(f) e7 i/o(f) g4 i/o(g) l5 v cc n26 i/o(d) a14 i/o(e) c11 i/o(f) e 8 v cc g5 i/o(g) l6 v cc p1 i/o(h) a15 i/o(e) c12 i/o(f) e9 i/o(f) g6 v ccio (g) l11 gnd p2 i/o(h) a16 i/o(e) c1 3 clk(7) e10 i/o(f) g21 v ccio (d) l12 gnd p 3 i/o(h) a17 i/o(e) c14 i/o(e) e11 i/o(f) g22 i/o(d) l1 3 gnd p4 v cc a1 8 ioctrl(e) c15 i/o(e) e12 v cc g2 3 i/o(d) l14 gnd p5 i/o(h) a19 ioctrl(e) c16 i/o(e) e1 3 i/o(f) g24 i/o(d) l15 gnd p6 v ccio (h) a20 i/o(e) c17 i/o(e) e14 i/o(f) g25 i/o(d) l16 gnd p11 gnd a21 i/o(e) c1 8 i/o(e) e15 i/o(e) g26 inref(d) l21 v cc p12 gnd a22 i/o(e) c19 i/o(e) e16 v cc h1 i/o(g) l22 i/o(d) p1 3 gnd a2 3 i/o(e) c20 i/o(e) e17 clk(6) h2 i/o(g) l2 3 i/o(d) p14 gnd a24 i/o(e) c21 i/o(e) e1 8 i/o(e) h 3 ioctrl(g) l24 i/o(d) p15 gnd a25 pllrst(1) c22 i/o(e) e19 i/o(e) h4 i/o(g) l25 i/o(d) p16 gnd a26 gnd c2 3 i/o(e) e20 i/o(e) h5 i/o(g) l26 i/o(d) p21 v ccio (c) b1 i/o(f) c24 i/o(e) e21 i/o(e) h6 v cc m1 i/o(g) p22 i/o(c) b2 pllrst(0) c25 i/o(e) e22 i/o(e) h21 v cc m2 i/o(g) p2 3 v cc b 3 i/o(f) c26 i/o(e) e2 3 gndpll(1) h22 v cc m 3 i/o(g) p24 i/o(c) b4 i/o(f) d1 i/o(g) e24 i/o(e) h2 3 i/o(d) m4 i/o(g) p25 i/o(c) b5 i/o(f) d2 i/o(g) e25 i/o(d) h24 ioctrl(d) m5 i/o(g) p26 trstb b6 i/o(f) d 3 i/o(f) e26 i/o(d) h25 ioctrl(d) m6 v ccio (g) r1 i/o(h) b7 ioctrl(f) d4 i/o(f) f1 ioctrl(g) h26 i/o(d) m11 gnd r2 i/o(h) b 8 i/o(f) d5 gndpll(0) f2 i/o(g) j1 i/o(g) m12 gnd r 3 i/o(h) b9 i/o(f) d6 i/o(f) f 3 i/o(g) j2 i/o(g) m1 3 gnd r4 i/o(h) b10 i/o(f) d7 i/o(f) f4 i/o(g) j 3 i/o(g) m14 gnd r5 v cc b11 i/o(f) d 8 i/o(f) f5 i/o(f) j4 i/o(g) m15 gnd r6 v cc b12 i/o(f) d9 i/o(f) f6 gnd j5 i/o(g) m16 gnd r11 gnd b1 3 clk(5) /pllin(3) d10 i/o(f) f7 v ccio (f) j6 v ccio (g) m21 v ccio (d) r12 gnd b14 i/o(e) d11 i/o(f) f 8 v cc j21 v ccio (d) m22 v cc r1 3 gnd b15 i/o(e) d12 i/o(f) f9 v ccio (f) j22 i/o(d) m2 3 i/o(d) r14 gnd b16 i/o(e) d1 3 tms f10 gnd j2 3 i/o(d) m24 i/o(d) r15 gnd b17 i/o(e) d14 i/o(e) f11 v cc j24 i/o(d) m25 i/o(d) r16 gnd b1 8 inref(e) d15 i/o(e) f12 v ccio (f) j25 i/o(d) m26 i/o(d) r21 v cc b19 i/o(e) d16 i/o(f) f1 3 gnd j26 i/o(d) n1 tck r22 i/o(c) b20 i/o(e) d17 i/o(e) f14 v ccio (e) k1 i/o(g) n2 i/o(h) r2 3 i/o(c) b21 i/o(e) d1 8 i/o(f) f15 v cc k2 i/o(g) n 3 i/o(g) r24 i/o(c) b22 i/o(e) d19 clk(8) f16 v cc k 3 i/o(g) n4 i/o(g) r25 i/o(c) b2 3 i/o(e) d20 i/o(e) f17 gnd k4 i/o(g) n5 i/o(g) r26 i/o(c) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 59 t1 i/o(h) v22 i/o(c) aa9 v ccio (a) ab20 i/o(b) ad5 i/o(a) ae16 i/o(b) t2 i/o(h) v2 3 i/o(c) aa10 gnd ab21 i/o(b) ad6 i/o(a) ae17 i/o(b) t 3 i/o(h) v24 ioctrl(c) aa11 v cc ab22 gndpll(2) ad7 i/o(a) ae1 8 i/o(b) t4 i/o(h) v25 i/o(c) aa12 v ccio (a) ab2 3 i/o(b) ad 8 ioctrl(a) ae19 i/o(b) t5 i/o(h) v26 i/o(c) aa1 3 gnd ab24 i/o(c) ad9 i/o(a) ae20 i/o(b) t6 v cc w1 inref(h) aa14 v ccio (b) ab25 i/o(c) ad10 i/o(a) ae21 i/o(b) t11 gnd w2 i/o(h) aa15 v cc ab26 i/o(c) ad11 i/o(a) ae22 i/o(b) t12 gnd w 3 i/o(h) aa16 v cc ac1 i/o(a) ad12 tdi ae2 3 i/o(b) t1 3 gnd w4 i/o(h) aa17 gnd ac2 i/o(a) ad1 3 clk(4) dedclk/pl lin(0) ae24 i/o(b) t14 gnd w5 v cc aa1 8 v ccio (b) ac 3 i/o(a) ad14 i/o(a) ae25 pllrst(2) t15 gnd w6 v cc aa19 v cc ac4 i/o(a) ad15 i/o(b) ae26 i/o(b) t16 gnd w21 v cc aa20 v ccio (b) ac5 i/o(a) ad16 i/o(b) af1 i/o(a) t21 v cc w22 i/o(c) aa21 gnd ac6 i/o(a) ad17 i/o(b) af2 i/o(a) t22 v cc w2 3 i/o(c) aa22 v cc pll(2) ac7 i/o(a) ad1 8 inref(b) af 3 i/o(a) t2 3 i/o(c) w24 i/o(c) aa2 3 i/o(c) ac 8 i/o(a) ad19 i/o(b) af4 i/o(a) t24 i/o(c) w25 inref(c) aa24 i/o(c) ac9 i/o(a) ad20 i/o(b) af5 i/o(a) t25 i/o(c) w26 i/o(c) aa25 i/o(c) ac10 i/o(a) ad21 i/o(b) af6 ioctrl(a) t26 i/o(c) y1 i/o(h) aa26 i/o(c) ac11 i/o(a) ad22 i/o(b) af7 i/o(a) u1 i/o(h) y2 i/o(h) ab1 i/o(h) ac12 i/o(a) ad2 3 i/o(b) af 8 i/o(a) u2 i/o(h) y 3 i/o(h) ab2 i/o(h) ac1 3 i/o(a) ad24 gnd af9 i/o(a) u 3 i/o(h) y4 i/o(h) ab 3 i/o(a) ac14 clk(1) ad25 i/o(b) af10 i/o(a) u4 i/o(h) y5 i/o(h) ab4 gndpll(3) ac15 i/o(b) ad26 i/o(b) af11 i/o(a) u5 i/o(h) y6 v ccio (h) ab5 v cc pll(3) ac16 i/o(b) ae1 gnd af12 clk(2) /pllin(2) u6 gnd y21 v ccio (c) ab6 i/o(a) ac17 i/o(b) ae2 gnd af1 3 i/o(b) u21 gnd y22 i/o(c) ab7 i/o(a) ac1 8 i/o(b) ae 3 i/o(a) af14 i/o(b) u22 i/o(c) y2 3 i/o(c) ab 8 i/o(a) ac19 i/o(b) ae4 i/o(a) af15 i/o(b) u2 3 i/o(c) y24 i/o(c) ab9 i/o(a) ac20 i/o(b) ae5 i/o(a) af16 i/o(b) u24 i/o(c) y25 i/o(c) ab10 i/o(a) ac21 i/o(b) ae6 i/o(a) af17 i/o(b) u25 i/o(c) y26 ioctrl(c) ab11 v cc ac22 tdo ae7 inref(a) af1 8 i/o(b) u26 i/o(c) aa1 i/o(h) ab12 i/o(a) ac2 3 pllout(1) ae 8 i/o(a) af19 ioctrl(b) v1 i/o(h) aa2 i/o(h) ab1 3 i/o(a) ac24 i/o(b) ae9 i/o(a) af20 ioctrl(b) v2 ioctrl(h) aa 3 i/o(h) ab14 clk(3)/ pllin(1) ac25 i/o(b) ae10 i/o(a) af21 i/o(b) v 3 ioctrl(h) aa4 i/o(a) ab15 v cc ac26 i/o(c) ae11 i/o(a) af22 i/o(b) v4 i/o(h) aa5 i/o(a) ab16 i/o(b) ad1 i/o(a) ae12 clk(0) af2 3 i/o(b) v5 i/o(h) aa6 gnd ab17 i/o(b) ad2 pllout(2) ae1 3 i/o(b) af24 i/o(b) v6 v ccio (h) aa7 v ccio (a) ab1 8 i/o(b) ad 3 pllrst(3) ae14 i/o(b) af25 i/o(b) v21 v ccio (c) aa 8 v cc ab19 v cc ad4 i/o(a) ae15 i/o(b) af26 i/o(b) table 36: 516 pbga pinout table (continued) pbga function pbga function pbga function pbga function pbga function pbga function www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 60 20 8 pqfp packaging drawing ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 61 2 8 0 lfbga packaging drawing www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 62 4 8 4 pbga packaging drawing ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 6 3 516 pbga packaging drawing www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? eclipseplus family data sheet rev. a 64 ordering information packaging information the eclipseplus product family packaging in formation is presented in table 3 7 . contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932 57 9011 (europe ? except german y/benelux) +(49) 89 930 86 170 (germany/benelux) +(86) 21 6867 0273 (asia ? except japan) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com table 37: packaging options device information device ql7100 ql7120 ql7160 ql71 8 0 pin pitch pin pitch pin pitch pin pitch package definitions a a. pqfp = plastic quad flat pack pbga = plastic ball grid array lfbga = low profile fine pitch ball grid array 208 pqfp 0.50 mm 208 pqfp 0.50 mm 280 lfbga 0.80 mm 280 lfbga 0.80 mm 280 lfbga 0.80 mm 280 lfbga 0.80 mm 484 pbga 1.0 mm 484 pbga 1.0 mm 484 pbga 1.0 mm 484 pbga 1.0 mm 516 pbga 1.27 mm 516 pbga 1.27 mm ql 71 8 0 - 4 pb516 c q u icklogic device eclip s epl us device p a rt n u m b er: 7100 7120 7160 71 8 0 s peed gr a de 4 = q u ick 5 = f as t 6 = f as ter 7 = f as te s t oper a ting r a nge c = commerci a l i = ind us tri a l m = milit a ry p a ck a ge code pt2 8 0 = 2 8 0-pin lfbga (0. 8 mm) pq20 8 = 20 8 -pin pqfp (0.5 mm) p s 4 8 4 = 4 8 4-pin pbga (1.0 mm) pb516 = 516-pin pbga (1.27 mm) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? eclipseplus family data sheet rev. a 65 revision history copyright and trademark information copyright ? 2006 quicklogic corpor ation. all rights reserved. the information contained in this document is protected by copyright. all righ ts are reserved by quicklogic corporation. quickl ogic corporation reserves the right to modify this document without an y obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized rep resentative of quicklogic is prohibited. quicklogic and the quicklogic logo, quickpci and quickworks are registered trademarks of quicklogic corporation. all trademarks and registered trademarks ar e the property of their respective owners. revision date originator and comments rev a february 2006 mehul kochar and kathleen murchek |
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